Revision History
The following table shows the revision history for this document.
Date Version Revision
3/18/2020 1.14Updated Table2-1, Table3-4, and Table4-1 XCVU19P (FSVA3824 and FSVB3824 packages) to production.
Chapter5: Updated definitions in Table5-1 for when the bar code contains the mark information. Updated Figure5-1, Figure5-2, Figure5-3, and Figure5-4 with the updated mark images.
Chapter7: Added the Typical Conditions for IR Reflow Soldering of Ceramic Column Grid Array Packages section. Updated the Pb-Free Reflow Soldering section including adding Table7-2 and Table7-3, changes to Table7-4 (mass reflow), heating rate recommendations, and other discussions including adding photos of thermocouples. Updated the Conformal Coating recommendation. Added a Strain Gauge Measurement section, moved and updated the Solder Paste section, and added the Component Placement section.
Chapter8: Updated the BGA Packages section, added the Stencil section, and moved the Solder Pa
沃尼希密码ste section.70 YEARS OF CHINA
Chapter9: Added the Component Clearance Surrounding Edge Bond section and updated the Edge Bond Removal section.
Chapter11: Updated the Applied Pressure from Heat Sink to the Package via Thermal Interface Materials section.
9/27/2019 1.13Added XCVU19P (FSVA3824 and FSVB3824 packages). Added the XCVU45P (FSVH2104 and FSVH2892) and XCVU47P (FSVH2892) devices/package combinations to appropriate tables and chapters.
Chapter1: Added Table1-8: I/O Bank Migration for VU19P devices: HP I/O Banks are Unshaded and HD I/O Banks are in Dark Gray. Updated Figure1-114 GTY Quad power supply designations on the right side.
Chapter3: Updated Figure3-151, Figure3-152, Figure3-153, and Figure3-154. Chapter7: Revised the maximum peak temperature range from 240°C–250°C to 245°C–250°C.
Chapter8: Updated discussions, added the Bull’s Eye Stencil Recommendation section with Figure8-
3 and the Solder Paste section.
Chapter9: Added chapter.
8/25/2017 1.8Chapter1, Packaging Overview: In Table1-4, corrected (increased) the available HP I/O pin counts for the XCKU095-FFVB2104. In Table1-5, revised the VCCINT_IO description. In Table1-7, updated the XCKU5P-FFVB676 mapping and added the XCKU095-FFVC1517. Added at Tip on page57. Updated bank designations in Figure1-8, Figure1-13, Figure1-15, Figure1-28, Figure1-32, Figure1-35, all XCVU080 Bank Diagrams, XCVU095 Bank Diagrams, Figure1-52, XCKU9P Bank Diagrams, Figure1-79, XCKU13P Bank Diagrams, and XCKU15P and XQKU15P Bank Diagrams.
Chapter2, Package Files: Updated links and package designations in Table2-1. Chapter3, Device Diagrams: Updated package designations in Table3-3 and Table3-4. Added Figure3-91 and Figure3-92. Updated Figure3-95 and Figure3-96. Added Figure3-113, Figure3-114, Figure3-127, Figure3-128, Figure3-135, and Figure3-136.
Chapter4, Mechanical Drawings: Updated package designations in Table4-1. Chapter5, Package Marking: Updated the Top Marks for Figure5-1 and Figure5-2 to show the date code and lot number
on the bar code version. Added package types to Table5-1.
Chapter6, Packing and Shipping: Added package types to Table6-1.
Chapter7, Soldering Guidelines: Added guidelines for lidless packages with stiffener ring and updated Table7-1. Revised the Mass Reflow from 250°C to 245°C on a number of package types in Table7-4. Revised Figure7-3 with new guidelines. Chapter10, Thermal Specifications: Added package types to Table10-1.
Added Documentation Navigator and Design Hubs in Appendix A.
4/27/2017 1.7.1Replaced the FFVE1760 (XCKU15P) figures in Chapter3, Device Diagrams.
4/26/2017 1.7Added the XQKU040, XQKU060, XQKU095, and XQKU115 devices where applicable. Added the RBA676, RFA1156, RLD1517, and RLF1924 packages where applicable. Chapter1, Packaging Overview: Updated Note5 in Table1-5. Revised Table1-6, Table1-7, and Table1-9. Added notes and recommendations to the SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated Blocks section. Revised many of the Device Diagrams.
Chapter2, Package Files: Updated the links. Added and updated package files for Virtex UltraScale+
and Kintex UltraScale+ FPGAs.
Chapter3, Device Diagrams: Added and updated diagrams for Virtex UltraScale+ and Kintex UltraScale+ FPGAs.
Chapter4, Mechanical Drawings: Added and replaced many of the mechanical drawings for the Virtex UltraScale+ and Kintex UltraScale+ devices.
Chapter5, Package Marking: Updated the Virtex UltraScale and Kintex UltraScale device top-mark diagrams to include the bar code top-mark diagrams. Added the Virtex UltraScale+ and Kintex UltraScale+ device top-mark diagrams.
Chapter7, Soldering Guidelines: Added the Sn/Pb Reflow Soldering section. Updated the Conformal Coating recommendation.
Date Version Revision
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9/04/2014 1.1
Added a discussion on ULA materials on page 16. In Differences from Previous Generations , updated the differential clock pin pairs and the VREF pin discussion. Added the Virtex UltraScale FPGA packages to Table 1-1. Also added the Virtex UltraScale devices to Table 1-2, Table 1-4, and Table 1-6. Updated PERSTN[0 to 1], DOUT_CSO_B , FWE_FCS2_B , RS[0 to 1], RDWR_FCS_B_0, D00_MOSI_0, D01_DIN_0, and VREF_[bank number] descriptions. Updated Multi-gigabit Serial Transceiver Pins (GTHE3 and GTYE3) pin names. Added Table 1-7 and Table 1-9. Revised the T[0 to 3][U or L ] and N[0 to 12] descriptions in the User I/O Pins section of Table 1-5: Pin Definitions . Updated the figures and added tables to the Die Level Bank Numbering Overview section.
Changed the TXT and CSV files associated with Table 2-1. Also updated Table 2-1 with additional device/packages and links.任楼论坛 In Chapter 3, Device Diagrams , replaced or added figures.
Added Figure 4-1 through Figure 4-4. Replaced Figure 4-12 and Figure 4-13. Added Figure 4-18 through Figure 4-13.
人体之最Added the Virtex UltraScale device package marking template to Chapter 5.Clarified the maximum reflow soldering guidelines on page 419 and updated Table 7-4: Peak Package Reflow Body Temperature(1). Replaced Figure 7-3. Removed the Sn/Pb Reflow Soldering section from Chapter 7, Soldering Guidelines . Added Post Reflow/Cleaning/Washing and Conformal Coating sections.
Updated Thermal Management Options and Figure 10-2. Added Heat Sink Removal and Package Pressure Handling Capacity to Chapter 11.
Updated the links to references [Ref 21], [Ref 22], and [Ref 23] in Appendix A . Added further references.
12/10/2013 1.0Initial Xilinx release.
2014山东
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