应用笔记
U-100A
U-100A
APPLICATION NOTE
UC3842/3/4/5 PROVIDES LOW-COST
CURRENT-MODE CONTROL
INTRODUCTION
CURRENT-MODE CONTROL
The fundamental challenge of power supply design is to simultaneously realize two conflicting objectives: good electrical performance and low cost. The is an integrated pulse width modulator designed with both these objectives in mind. This provides de-signers an inexpensive controller with which they can ob-tain all the performance advantages of current mode op-eration. In addition, the U
C3842 series is optimized for ef-ficient power sequencing of off-line converters, DC to DC regulators and for driving power MOSFETs or transistors.
This application note provides a functional description of the UC3842 family and highlights the features of each in-dividual member, the UC3842, UC3843, UC3844 and UC3845 Throughout the text, the UC3842 part number will be referenced, however the generalized circuits and performance characteristics apply to each member of the UC3842 series unless otherwise noted. A review of cur-rent mode control and its benefits is included and meth-ods of avoiding common pitfalls are mentioned. The final section presents designs of power supplies utilizing UC3842 control.
Figure 1 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal initi-ates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold established by the error signal. In this
way the error signal actually controls peak inductor cur-rent. This contrasts with conventional schemes in which the error signal directly controls pulse width without regard to inductor current.
Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward characteristic is achieved; i.e., the control circuit instanta-neously corrects for input volt
age variations without using up any of the error amplifier’s dynamic range. Therefore,line regulation is excellent and the error amplifier can be dedicated to correcting for load variations exclusively.For converters in which inductor current is continuous,controlling peak current is nearly equivalent to controlling average current. Therefore, when such converters employ current-mode control, the inductor can be treated as an
Figure 1. Two-Loop Current-Mode Control System
UC3842/3/4/5提供了低成本的电流模式控制
引言
电源设计的主要难题是需要同时实现两个相互矛盾的目标，即：上佳的电性能和低成本。UC3842/3/4/5是一款集成脉宽
调制器 (PWM)，它在设计时兼顾了上述的两个目标。该IC颈部肿块的鉴别诊断
为设计师提供了一款廉价的控制器，他们借助该控制器能够获得电流模式操作的所有性能优势。此外，UC3842系列还专为隔离式转换器和DC-DC 稳压器的高效电源排序以及功率MOSFET 或晶体管的驱动进行了优化。
本应用笔记提供了UC3842系列的功能描述，并突出介绍了其每个成员 (UC3842、UC3843、UC3844和UC3845) 的特点。文章通篇以型号为UC3842的器件为参考，不过，除非特别注明，否则一般化的电路和性能特征将适用于UC3842系列的所有成员。本文评述了电流模式控制及其好处，并提及了避免常见易犯错误的方法。最后的章节给出了运用UC3842控制器的电源设计方案。电流模式控制
图1示出了双环路电流模式控制系统在典型降压型稳压器中的应用。时钟信号以一个固定频率来启动电源脉冲。当电感器电流的模拟量达到由误差信号所确定的门限时，脉冲将被终止。误差信号以这种方式实际上起到了控制峰值电感器电流的作用。这与传统方案截然不同，后者是由误差信号直接控制 脉冲宽度，而不考虑电感器电流。通过使用电流模式控制获得了的一些性能优势。首先，实现了一种输入电压前馈特性；即：控制电路能够即刻校正输入电压偏差，而不会耗尽任何误差放大器的动态范围。因此，线路输入电压调节性能非常出，而且误差放大器可被指定专门用于校正负载偏差。
对于那些具有连续电感器电流的转换器而言，控制峰值电流式控制时，可将电感器视作一个误差电压控制型电流源，以
便进行小信号分析。（接下页）member, the UC3842, UC3843, UC3844 and 图1：双环路电流模式控制系统
应用笔记
U-100A
坂茂-100A
APPLICATION NOTE
U-100A
error-voltage-controlled-current-source for the purposes of small-signal analysis. This is illustrated by Figure 2. The
two-pole control-to-output frequency response of these converters is reduced to a single-pole (filter capacitor in parallel with load) response. One result is that the error amplifier compensation can be designed to yield a stable closed-loop converter response with greater gainband-width than would be possible with pulse-width control, giv-ing the supply improved small-signal dynamic response to changing loads. A second result is that the error amplifier compensation circuit becomes simpler, as illustrated in Fig-ure 3. Capacitor and resistor in Figure 3a add a low frequency zero which cancels one of the two control-to-.output poles of non-current-mode converters. For large-signal load changes, in which converter response is limit-ed by inductor slew rate, the error amplifier will saturate while the inductor is catching up with the load. During this time, will charge to an abnormal level. When the induc-tor current reaches its required level, the voltage on causes a corresponding error in supply output voltage.
The recovery time is which may be quite long. How-ever, the compensation network of Figure can be used where current-mode control has eliminated the inductor pole. Large-signal dynamic response is then greatly im-proved due to the absence of
Current limiting is greatly simplified with current-mode con-trol. Pulse-by-pulse limiting is, of course, inherent in the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensur-ing reliable supply operation.
Finally, current-mode controlled power stages can be op-erated in parallel with equal current sharing. This opens the possibility of a modular approach to power supply de-sign.
Figure 2. Inductor Looks Like a Current Source to Small Signals
A) Direct Duty Cycle Control B) Current Mode Control Figure 3. Required Error Amplifier Compensation for Continuous Inductor Current Designs （接上页）这一点示于图2。这些转换器的双极点控制－输出频率响应被简化为一个单极点（滤波电容器与负载并联）响应。一个结果是：可以通过设计使误差放大器补偿产生稳定的闭环转换器响应和较大的增益带宽（相比于采用脉宽控制时），从而改善了电源对于变化中的负载的小信号动态响应。第二个结果是误差放大器补偿电路变得简单了，如图3所示。图3a 中的电容器C i 和电阻器Riz 增添了一个低频零点，该零点信号负载变化（这里，转换器响应受限于电感器转换速率），当电感器的阻抗逐步赶上负载时，误差放大器将发生饱和。在这段时间里，C i 将充电至一个异常的水平。当电感器电流达到其所需的水平时，C i 上的电压将在电源输出电压中引起一个对应的误差。恢复时间为R iz C i ，该时间有可能相当长。然而，在电流模式控制已经消除了电感器极点的场合中，可以采用图3b 中的补偿网络。由于不存在C i
，因此大信号动态响应得到了极
大的改善。
电流模式控制的运用大大地简化了电流限制。在该控制方案中，逐个脉冲电流限制当然是固有的特征。而且，通过简单地对误差电压进行箝位，即可确定峰值电流的上限。准确的电流限制可实现磁性元件和功率半导体元件的优化，并确保可靠的电源操作。
最后，电流模式控制功率级可以与均流电路并联运作。这为实现模块化的电源设计方法提供了可能性。
图2：电感器看起来像是一个至小信号的电流源A) 直接占空比控制B) 电流模式控制
图3：连续电感器电流设计所需的误差放大器补偿
应用笔记
U-100A
APPLICATION NOTE
U-100A
THE UC3842/3/4/5 SERIES OF CURRENT-MODE PWM IC’S
DESCRIPTION
FEATURES
The UC1842/3/4/5 family of control ICs provides the nec-essary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal
external parts count. Internally implemented circuits in-clude under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control,and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving ei-
ther N Channel MOSFETs or bipolar transistor switches, is low in the off state.
Differences between members of this family are the un-der-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-tions. The corresponding thresholds for the UC1843 and UC1845 are 8.5V and 7.9V. The UC1842 and UC1843 can
音调控制电路operate to duty cycles approaching 100%. A range of zero to <50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flip which blanks the output off every other clock cycle.
IC SELECTION GUIDE Optimized for Off-Line and DC to DC Converters
Low Start Up Current (< 1 mA)
Automatic Feed Forward Compensation Pulse-By-Pulse Current Limiting Enhanced Load Response Characteristics Under-Voltage Lockout with Hysteresis
Double Pulse Suppression High Current Totem Pole Output
Internally Trimmed Bandgap Reference 500 kHz Operation Low Error Amp RECOMMENDED USAGE
周洋感谢门
斯巴克胆机
Note: 1. A= DIL-8 Pin Number. B = SO-16 Pin Number.
2. Toggle flip flop used only in 1844A and 1845A.
Figure 4UC3842/3/4/5系列电流模式PWM IC 描述
UC1842/3/4/5
系列控制IC 提供了利用极少的外部元件来实现隔离式或DC/DC 固定频率电流模式控制方案所必需的特点。在内部实现的电路包括启动电流小于1mA 的欠压闭锁电路、一个精准的基准（经过修整以在误差放大器输入端上提供高准确度）、用于确保闭锁操作的逻辑电路、一个另外还提供了电流限值控制功能的PWM 比较器、以及一个专为供应或吸收高峰值电流而设计的图腾柱输出级。这个适合于驱动N 沟道MOSFET
或双极晶体管开关的输出级在关断状态中为低电平。该系列各成员之间的差异在于欠压闭锁门限和最大占空比范围。UC1842和UC1844具有16V （接通）和10V （关断）的UVLO
门限，非常适合于隔离式应用。UC1843和UC1845的对应门限为8.5V 和7.9V 。UC1842和UC1843能
够在占空比接近100%的条件下运作。通过增设一个内部电平转换触发器（它每隔一个时钟周期将输出关闭），UC1844和UC1845获得了0%至＜50%的占空比范围。特点专为隔离式和DC-DC 转换器而优化低启动电流 (＜1mA)自动前馈补偿逐个脉冲电流限制
增强的负载响应特性
具迟滞的欠压闭锁
双脉冲抑制高电流图腾柱输出
在内部修整的带隙基准500kHz 工作频率低RO 误差放大器
•••••••••••IC
选择指南推荐的用法图4
应用笔记网络采集
U-100A
-100A
APPLICATION NOTE
U-100A is adequate to make fully operational before enabling the output stage. Figure that the turn-off thresholds internally oscillations shows supply than 1 cient bootstrapping from the rectified input of an off-line and must be charged to 16V through With a start-up current of 1 can be as large as 100 and still charge GIN when =90V RMS (low line). Power dissipation in would then be less than 350 mW even under high line = 130V During UVLO; the output driver is in a low state. While it doesn’t exhibit the same saturation characteristics as nor-Figure 6. During Under-Voltage Lockout, the output
driver is biased to sink minor amounts of
current.
OSCILLATOR The UC3842 oscillator is programmed as shown in Figure
8. Timing capacitor CT is charged from (5V) through
by an selecting and oscillator combinations versus oscillator frequency. The timing resistor can be cal- The UC3844 UC3845 have an internal flip-flop oscillator for a 50% kHz.
Figure 7. Providing Power to the
0019-8
图6：在欠压闭锁期间，对输出驱动器施加了偏压，以吸收较少量的电流。UVLO 电路用于确保V 足以在启用输出级之前使全面运作。如图5所示，接通和关断门限分别在内部固迟滞用于防止在电源排序期间发生示出了电源电流要求。由于能够从一个隔离式转换器的整流输入实现高效的自举，因此启动电流小于产生。然而，在启动时，充电至16V 。由于启动电流为1mA 的阻值最大可至100k Ω，而AC = 90VRMS （低线路输入电压）时仍然对进行充RIN 中的功耗于是将小于350mW ，即使在高线路输入电压(V AC = 130VRMS) 条件下也不例外。
在UVLO 期间；输出驱动器处于低电平状态。尽管它所呈现的饱和特性与正常操作时有所不同，但它仍然能够很容易地吸收1mA
的电流，这足以确保振荡器
UC3842振荡器的设置如图8所示。定时电容器CT 通过定时电RT V (5V) 来充电，并由一个内部电流源进行放电。在选择振荡器元件的过程中，第一步是确定所需的电路死区时T R T /C 组合与振荡器频率的关系曲线。定时电阻器的阻值可以由下式来计算。UC3844
具有一个由振荡器来驱动的内部二分频触发器，以提供一个50%的最大占空比。因此，必须将其振荡器的运行频率设定为期望的电源开关频率的两倍。APPLICATION NOTE U-100A that the turn-off thresholds internally spectively. The 6V hysteresis prevents during power sequencing. Figure 6 than 1 cient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 6. During normal circuit auxiliary winding to 16V With a start-up current of 1 can be as large as 100 and still charge GIN when =90V RMS (low line). Power dissipation in would then be less than 350 mW even under high line = 130V RMS) conditions.During UVLO; the output driver is in a low state. While it doesn’t exhibit the same saturation characteristics as nor-mal operation, it can easily sink 1 milliamp, enough to in-sure the MOSFET is held off.Figure 6. During Under-Voltage Lockout, the output
driver is biased to sink minor amounts of
current.OSCILLATOR The UC3842 oscillator is programmed as shown in Figure 8. Timing capacitor CT is charged from (5V) through the timing resistor and discharged by an internal cur-rent source.selecting oscillator components required deadtime. Once Figure 9 is used to pinpoint the nearest standard value of combinations versus oscillator frequency. The timing resistor can be cal-The UC3844 UC3845 have an internal flip-flop oscillator for a 50% cycle. Therefore, their oscillators
must be set to run at twice power supply switching Figure 7. Providing Power to the
0019-8
图7：给UC3842/3/4/5供电
Rin.max=(Vin.min-16)/而言，此处的启动电流取定时电阻与定时电容选择时，可考虑相关的占空比限制
应用笔记
U-100A
APPLICATION NOTE
MAXIMUM DUTY CYCLE The UC3842 and UC3843 have a maximum duty cycle of approximately 100%, whereas the UC3844 and UC3845are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most fly-
back and forward converters. For optimum IC perform-ance the deadtime
should not exceed 15% of the oscilla-tor clock period.
During the discharge, or “dead” time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle to: = 1 - U C 3842/3 = 1 - / 2 X UC3844/5where T PERIOD = 1 / F oscillator
0019-9
Figure
8Deadtime vs > 5k)
Figure 9Timing Resistance vs Frequency
0019-10
FREOUENCY - (Hz)
0019-11
Figure 10
U-100A
CURRENT SENSING AND
LIMITING The UC3842 current sense input is configured as shown in Figure 12. Current-to-voltage conversion is done exter-nally with ground-referenced resistor Under normal operation the peak voltage across is controlled by the E/A according to the following relation:
where = control voltage = E/A output voltage.
can be connected to the power circuit directly or through a current transformer, as Figure 11 illustrate
s.While a direct connection is simpler, a transformer can re-duce power dissipation in reduce errors caused by the base current, and provide level shifting to eliminate the re-straint of ground-referenced sensing. The relation be-tween and peak current in the power stage is given by:
where: N = current sense transformer turns ratio
= 1 when transformer not used.For purposes of small-signal analysis, the control-to-sensed-current gain is:
When sensing current in series with the power transistor,as shown in Figure 11, the current waveform will often have a large spike at its leading edge. This is due to recti-fier recovery and/or inter-winding capacitance in the pow-er transformer. If unattenuated, this transient can prema-turely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the cur-rent spike duration (usually a few hundred nanoseconds).The inverting input to the UC3842 current-sense compara-tor is internally clamped to 1V (Figure 12). Current limiting occurs if the voltage at pin 3 reaches this threshold , the current limit is defined by:
0019-13
Figure 11. Transformer-Coupled Current Sensing
最大占空比
UC3842和UC3843具有约100%的最大占空比，而UC3844和UC3845
的最大占空比则被一个内部电平转换触发器箝位于50%
。在大多数反激式和正激式转换器中，这种占空比箝位是有好处的。为了获得最佳的IC 性能，死区时间不应超过振荡器时钟周期的15%。在放电期间（或“死区”时间）里，内部时钟信号将输出锁至低电平状态。这将最大占空比DMAX 限制为：D MAX = 1 – (t
DEAD / t PERIOD ) UC3842/3D MAX = 1 – (t DEAD / 2 x t PERIOD ) UC3844/5式中的t DEAD = 1 / F 振荡器
死区时间与CT 的关系曲线 (RT ＞5k)图8定时电阻与频率的关系曲线图9图10电流检测和限制UC3842电流检测输入的配置如图12所示。电流－电压转换利用接地参考电阻器R S 在外部完成。在正常工作条件下，RS 两端的峰值电压受控于E/A （误差放大器），依据的公式如下：
(V C – 1.4V)
(3 R S )
式中，V C = 控制电压 = E/A 输出电压。如图11所示，RS 可直接（或通过一个电流变压器）连接至电源电路。虽然直接连接的做法比较简单，但采用变压器能够降低RS 中的功耗、减少由基极电流引起的误差、并提供电平移位以消除接地参考检测的限制。VC 与功率级中的峰值电流之间的关系由下式给出：
V R S(pk) N
RS 3R S
式中：N = 电流检测变压器匝数比 = 1
（当未使用变压器时）。为了便于小信号分析，控制－检测电流增益为： i (pk) N
V C 3 R S
如图11所示，当检测与功率晶体管串联的电流时，电流波形在其前沿处常常将出现一个很大的尖峰。这是由于整流器恢复和/或电源变压器中的绕组间电容所造成的。如果不对其进行衰减，那么该瞬变会
过早地终止输出脉冲。如图所示，采用一个简单的RC 滤波器往往足以抑制该尖峰。RC 时间常数应大致等于电流尖峰持续时间（通常为几百ns ）。UC3842电流检测比较器的反相输入在内部箝位于1V （图12）。如果引脚3上的电压达到其门限值，则电流限制电路开始起作用，也就是说：电流限值由下式决定： N x 1V
RS
I P =
i (pk) = N ( V C – 1.4V )()
=
= i max =
APPLICATION NOTE MAXIMUM DUTY CYCLE
The UC3842 and UC3843 have a maximum duty cycle of approximately 100%, whereas the UC3844 and UC3845are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most fly-back and forward converters. For optimum IC perform-ance the d
eadtime should not exceed 15% of the oscilla-tor clock period.During the discharge, or “dead” time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle to: = 1 - U C 3842/3 = 1 - / 2 X UC3844/5where T PERIOD = 1 / F oscillator 0019-9
Figure 8
Deadtime vs > 5k)
Figure 9
Timing Resistance vs Frequency 0019-10
FREOUENCY - (Hz)0019-11Figure 10U-100A
CURRENT SENSING AND LIMITING
The UC3842 current sense input is configured as shown in Figure 12. Current-to-voltage conversion is done exter-
nally with ground-referenced resistor Under normal
operation the peak voltage across is controlled by the E/A according to the following relation:where
= control voltage = E/A output voltage.
can be connected to the power circuit directly or through a current transformer, as Figure 11 illustrates.While a direct connection is simpler, a transformer can re-duce power dissipation in reduce errors caused by the base current, and provide level shifting to eliminate the re-straint of ground-referenced sensing. The relation be-tween and peak current in the power stage is given by:where: N = current sense transformer turns ratio
= 1 when transformer not used.For purposes of small-signal analysis, the control-to-sensed-current gain is:
When sensing current in series with the power transistor,as shown in Figure 11, the current waveform will often
have a large spike at its leading edge. This is due to recti-fier recovery and/or inter-winding capacitance in the pow-er transformer. If unattenuated, this transient can prema-turely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time c
onstant should be approximately equal to the cur-rent spike duration (usually a few hundred nanoseconds).The inverting input to the UC3842 current-sense compara-tor is internally clamped to 1V (Figure 12). Current limiting occurs if the voltage at pin 3 reaches this threshold , the current limit is defined by:
0019-13
Figure 11. Transformer-Coupled Current Sensing
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