Mater. Res. Soc. Symp. Proc. Vol. 989 © 2007 Materials Research Society0989-A03-04 High Open-Circuit Voltage in Silicon Heterojunction Solar Cells
Qi Wang1, Matt R Page1, Eugene Iwancizko1, Yueqin Xu1, Lorenzo Roybal1, Russell Bauer1, Dean Levi1, Yanfa Yan1, Tihu Wang2, and Howard M. Branz1杭州中泰
垃圾焚烧厂
1EDMD, National Renewable Eenergy Laboratory, Golden, CO, 80410
2Suntech Power, Wuxi, China, People's Republic of
ABSTRACT
High open-circuit voltage (V oc) silicon heterojunction (SHJ) solar cells are fabricated in double-heterojunction a-Si:H/c-Si/a-Si:H structures using low temperature (<225∞C) hydrogenated amorphous silicon (a-Si:H) contacts deposited by hot-wire chemical vapor deposition (HWCVD). On p-type c-Si float-zone wafers, we used an amorphous n/i contact to the top surface and an i/p contact to the back surface to obtain a V oc of 667 mV in a 1 cm2 cell with an efficiency of 18.2%. This is the best reported p-type SHJ voltage. In our labs, it improves over the 652 mV cell obtained with a front amorphous n/i heterojunction emitter and a high-temperature alloyed Al back-surface-field contact. On
n-type c-Si float-zone wafers, we used an a-Si:H (p/i) front emitter and an a-Si:H (i/n) back contact to achieve a V oc of 691 mV on 1 cm2 cell. Though not as high as the 730 mV reported by Sanyo on n-wafers, this is the highest reported V oc for SHJ c-Si cells processed by the HWCVD technique. We found that effective c-Si surface cleaning and a double-heterojunction are keys to obtaining high V oc. Transmission electron microscopy reveals that high V oc cells require an abrupt interface from c-Si to a-Si:H. If the transition from the base wafer to the a-Si:H incorporates either microcrystalline or epitaxial Si at c-Si interface, a low V oc will result. Lifetime measurement shows that the back-surface-recombination velocity (BSRV) can be reduced to ~15 cm/s through a-Si:H passivation. Amorphous silicon heterojunction layers on crystalline wafers thus combine low-surface recombination velocity with excellent carrier extraction.
INTRODUCTION
八宝煤矿
Open-circuit voltage (V oc) of crystal silicon (c-Si) solar cells on high-quality wafers (minority carrier diffusion length much greater than wafer thickness) is limited by the surface recombination rates. Any dark-current path through inadequately surface passivation reduces both V oc and the collection of photo-generated charge carriers. Therefore, surface passivation is the key to achieve high V oc and, ultimately, high-performance solar cells. The unique combination of surface passivation and cur
rent conduction of a-Si:H on c-Si allows superior a-Si:H/c-Si emitter construction as well excellent full-area a-Si:H/c-Si back contact creation [1], all at temperatures below 250∞C. The a-Si:H passivation is comparable to the dielectric surface passivation means such as SiO2 and SiN x but a-Si heterojunctions provide good current conduction without the fired-glass-frit or laser-fired contacts needed on these dielectric layers. Early, we reported our single heterojunction a-Si/c-Si (p-type) solar cells with V oc of 645 mV, an increase of 15 mV over a diffused junction emitter. Optimization of the i/n a-Si:H front emitter enable us to achieve 17.1%-efficient single-heterojunction solar cells with a screen-
printed Al back-surface field (BSF) [2]. However, an Al-BSF limits further improvements in our device performance, because of a high back-surface-recombination velocity (BSRV), on the order of 103 cm/sec. This causes a high back-surface dark saturation current component that limits the open-circuit voltage. Further, an Al-BSF has to be processed at temperatures above 800∫C and this may cause a problem to keep a clean front surface before the heterojunction deposition. Replacing the conventional Al-alloyed BSF on p-type wafers or P-diffused BSF on n-type wafers by the effective a-Si:H thin passivating layers will improve open-circuit voltage significantly [3] and also avoids all high-temperature processing steps.
This paper describes our progress in achieving this objective. We illustrate our systematic development of deposited a-Si:H as front emitters and back contacts by hot wire chemical vapor deposition (HWCVD) for both p- and n-type silicon wafers. In commonly used plasma-enhanced chemical vapor deposition (PECVD), great care must be taken to avoid plasma damage to the c-Si wafer surfaces to make high-efficiency SHJ cells; we opt to use HWCVD to grow a-Si:H layers to eliminate the possibility of such ion damage. For both doping types, we obtain higher open-circuit voltages than with standard Al-alloyed or P-diffused back-surface-field contacts. Our highest V oc is 691 mV on n-type c-Si.
雄心
飞扬EXPERIMENTAL
Open-circuit voltage and the interface-recombination velocity are the key indicators of the a-Si:H/c-Si heterointerface quality. Our work attempts to contribute to both the technological development of high-efficiency silicon heterojunction solar cells and the fundamental understanding of the a-Si:H/c-Si interface; therefore, we study both finished isolated solar cells of 1 cm2 in a structure of ITO/a-Si:H/c-Si/a-Si:H/Metal for complete device characterizations and as-deposited a-Si:H/c-Si/a-Si:H structures for evaluation lifetime using a Sinton lifetime tester and estimate BSRV from the measured lifetime. High-resolution transmission electron microscopy (HRTEM) is used to characteriz
e the structure of the a-Si/c-Si interface. Both high-quality p- and n-type float-zone silicon (FZ-Si) wafers, bulk lifetime greater than 1 ms, are used in this study. Exact details of sample preparation and a-Si:H deposition are given elsewhere [2-6].
RESULTS AND DISCUSSIONS
工商银行
山东省分行
We focus on the improvement of V oc using a-Si:H emitters to achieve high performance c-Si solar cells. With a diffused junction on p-type wafer solar cell having a V oc of 630 mV as the reference, the front-only single heterojunction SHJ cell on p-type wafer having a similar Al-BSF as diffused one shows an improved V oc of 652 mV. When
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Figure 1. Solar cell performance under AM 1.5 for double-heterojunction SHJ isolated 1 cm 2 cells based on both textured p -type (a) and planar n -type (b) wafers.
we optimize the thin HWCVD a-Si:H emitter layers, we can achieve a very low surface recombination velocity about 15 cm/sec [5]. We found that it is critical to obtain and maintain a clean interface before the thin Si emitter and avoid formation of epitaxial c-Si or nanocrystalline Si at the interface. In order to increase the cellís short-circuit current, J sc , we first used textured wafers with the same Al-BSF back contacts as the planar cells. An essentially identical V oc of 651 mV is obtained despite the much increased surface area due to roughness, indicating the near perfect front surface passivation by the a-Si:H(i/n ) emitter.
However, an Al-BSF has a back-surface-recombination velocity (BSRV) on the order of 103 cm/s, wh
ich causes a high back-surface saturation current component that limits further increases in V oc . In addition, an Al-BSF has to be processed at temperatures above 800∫C which could increase the impurity concentration at the front surface. To further improve the V oc , we replace the high-temperature Al-BSF with low-temperature HWCVD-deposited i/p a-Si:H layers as the back contact. Lifetime measurement shows the BSRV is reduced to ~15 cm/sec. We obtain a higher V oc of 676 mV on some devices, including even textured p -type silicon wafers in the double-heterojunction structure (front n/i heterojunction emitter and back i/p heterojunction contact).
On n -type wafers, we start with a planar a-Si:H p/i front emitter and a P-diffused BSF as the back contact. This gives an unimpressive V oc of 627 mV. However, once we replace the back P-diffused BSF with a-Si(i/n ) layers as the back contact, V oc jumps to 691 mV. This is the highest open-circuit voltage achieved using the HWCVD technique so far, implying a great potential in reaching very high-efficiency SHJ solar cells. Again, when we texture the wafer to increase J sc , a high V oc of 686 mV is attained.
Figure 2. Cell structure for double-heterojunction SHJ cells.
Figure 1 shows an J-V curve of a high V oc SHJ c-Si solar cells performance as measured by our un
official but calibrated simulator XT-10. Figure 1a is our double heterojunction SHJ device on textured p-type wafer with high efficiency over 18%.Fill factor is another important performance parameter for back contact quality. When using a dielectric back-surface passivation by insulating materials, one must employ local contact windows [7] to obtain low-resistance and effective majority carrier collection. On the other hand, with full-area back contacts of a-Si:H, it is possible to obtain excellent hole conduction across the back c-Si(p)/a-Si:H(i/p) interface; we obtain a good fill factor of 78%. We found that micro-crystalline p-layer [8] is not necessary. High-resolution transmission electron micrographs show that our back c-Si(p)/(i/p) interface is all amorphous [9] ñ clearly we can make our low-resistance contact with a-Si:H (i/p).
Figure 1b is the J-V curve of our double heterojunction SHJ device on planar n-type wafer. Currently we achieved a V oc of about 690 mV in the double side junction structure. This V oc is higher than on p-type wafers and shows the great potential to achieve even higher efficiency using textured n-type wafer. However, this cell had a low FF of 0.72. We believe it is due to a high series resistance at the back contact. After optimization, we have improved the FF to around 0.76. Certainly, there is still room to further enhance the electron transport across the c-Si (n)/a-Si:H(i/n) back contact.
We also found the metal contact to the a-Si:H back is important to obtaining high V oc. Figure 2 sho
ws two types of back metal contacts to the n-layer: a) one is using ITO and b) the other is using a metal such as Ti, with no ITO. Figure 3 shows the importance to V oc of which layer contacts the n-layer. We use an ITO contact to the n-layer (Fig. 2a) to establish the reference a V oc of 680 mV. Once we use Ti direct contact to the same n-layer (Fig. 2b), the V oc decreases to 56 mV. However, when we deposit a much thicker n-layer (6 times increased deposition time) and then the Ti contact, V oc is restored to close to 680 mV. This effect can be explained by the hypothesis of metal diffusion
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中国
农业生态学报
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V o c (m V )2
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Cell structure Figure 3. V oc as a function of various back contacts. 0: n /ITO/Ti, 1: n /Ti, 2: 6x n /Ti. Lines
between points are guided to eye.
through the thin BSF to the back c-Si interface which could cause a high BSRV and a decrease of V oc . A thicker n -layer can stop the diffusion of metal and maintain the high V oc . It is interesting to observe that ITO to n -layer has no such deleterious effect.
Finally, we discuss the effect of annealing of low temperature deposited a-Si:H on lifetime and BSRV. In recent report by De Wolf [10], the lifetime increased significantly by moderate annealing (~250∞C) for about 30 min of a-Si:H grown at 105∞C. Higher lifetime will normally produce a higher V oc . In our SHJ cell process, we grow the i -layer at 100∞C and the doped layers at higher temperature (below 225∞C) to avoid epitaxy and increase the doping efficiency. It is possible that we unintentionally anneal the i -layer during the heating and deposition of the doped layers. In our early report [5], we find our best growth condition to have a high lifetime and low BSRV is at 100∞C for i -layer without annealing and a high V oc with an abrupt interface at c-Si surface to a-Si. Higher temperature i -layer did not yield a high lifetime in contradict to De Wolfís work. We will continue work on the understanding of the high V oc .
CONCLUSIONS
We have successfully replaced the conventional high-temperature Al-BSF or P-diffused BSF with a-
Si:H back contacts in double heterojunction SHJ solar cells. Excellent a-Si/c-Si heterointerfaces at both front emitter and back contact with minimal
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