SIMPLE SWITCHER ®PCB Layout Guidelines
Introduction
One problem with writing an Application Note on PCB layout is that the people who read it are usually not the ones who are going to use it.Even if the designer has struggled through electromagnetic fields,EMC,EMI,board parasitics,transmission line effects,grounding,etc.,he will in all prob-ability then go on with his primary design task,leaving the layout to the CAD/layout person.Unfortunately,especially when it comes to switching regulators,it is not enough to be concerned with just basic routing/connectivity and mechani-cal issues.Both the designer and the CAD person need to be aware that the design of a switching power con-verter is only as good as its layout.Which probably ex-plains why a great many of customer calls received,con-cerning switcher a
pplications,are ultimately traced to poor layout practices.Sadly,these could and should have been avoided on the very first prototype board,saving time and money on all sides.
The overall subject of PCB design is an extremely wide one,embracing several test/mechanical/production issues and also in some cases compliance/regulatory issues.There is also a certain amount of physics/electromagnetics involved,if a clearer understanding is sought.But the purpose of this Application Note is to reach the audience most likely to use it.Though there is enough design information for the more
experienced designer/CAD person,the Application Note in-cludes a quick-set of clear and concise basic rules that should be scrupulously followed to avoid a majority of prob-lems.In particular,we have provided recommended start-ing points for layout when using the popular LM267x,LM259x and LM257x families (Figure 2)The focus is on the step-down (Buck)Simple Switcher ICs from National,but the same principles hold for any topology and switching power application.
Most of the issues discussed in this Note revolve around simply assuring the desired performance in terms of basic electrical functionality.Though luckily,as the beleaguered switcher designer will be happy to know,in general all the electrical aspects involved are related and point in the same general
‘direction’.So for example,an ‘ideal’ which helps the IC function properly,also leads to reduced electromagnetic emissions,and vice-versa.For example,reducing the area of loops with switching currents will help in terms of EMI and performance.However the designer is cautioned that there are some exceptions to this general ’trend’.One which is brought out in some detail here is the practice of ’copper-filling’,which may help reduce parasitic inductances and reduce noise-induced IC problems,but can also increase EMI.
Quick-Set of Rules for SIMPLE SWITCHER PCB Layout (Buck)
a)Place the catch diode and input capacitor as shown in Figure 2.
b)For high-speed devices (e.g.LM267x)do not omit placing input decoupling/bypass ceramic capacitor (0.1µF–0.47µF)as in Figure 2.
c)Connect vias to a Ground plane if available (optional,marked ‘X’in Figure 2)
d)If vias fall under tab of SMT power device,these are considered ‘thermal vias’.Use correct dimensions as discussed to avoid production issues.Or place the vias close to but not directly under the tab.
e)Route feedback trace correctly as discussed,away from noise sources such as the inductor and the diode.f)Do not increase width of copper on switching node injudiciously.
g)If very large heatsink area is required for catch diode (having estimated the heatsink requirement correctly)use isolation as discussed.
h)
For higher power SMT applications,use 2oz board for better thermal management with less copper area.
SIMPLE SWITCHER is a Registered Trademark of National Semiconductor.
神曲1 2
National Semiconductor Application Note 1229Sanjaya Maniktala July 2002
SIMPLE SWITCHER PCB Layout Guidelines
AN-1229
©2002National Semiconductor Corporation AN200426www.national
Introduction
(Continued)
The AC and DC Current Paths
Referring to Figure 1a ,the bold lines represents the main (power)current flow in the converter during the time the switch is ON.As the switch turns ON,the edge of the of the current waveform is provided largely by CBYPASS,the re-mainder coming mainly from CIN.Some slower current com-ponents come from the input DC power supply (not shown)and also refresh these input caps.Figure 1b represents the situation when the switch is OFF.We can therefore see that in certain trace sections,current has to start flowing sud-denly during the instant of switch turn-off and in some sec-tions it needs to stop flowing equally suddenly.Figure 1c represents the ‘difference’,aces shown bold in this Figure are those where the current flow changes suddenly .
During the turn-on transition the picture reverses,but the ’difference’trace sections are the same.Therefore during either switch transition,’step changes’of current take place in these difference sections.These traces encounter the harmonic-rich rising or trailing edges of the current pedestal waveform.The difference traces are considered ’critical’and deserve utmost attention during PCB layout.It is often stated colloquially,that ‘AC current’flows in these trace sections,and ’DC current’in the others.The reason is that the basic switching PWM frequency forms only a fraction of the total harmonic (Fourier)content of the current waveform in the ’AC’traces.In comparison,where ‘DC curren
t’flows,the current does not change in a stepped fashion and so the harmonic content is lower.It is also no surprise that the DC
20042601
FIGURE 1.
A N -1229
www.national
2
The AC and DC Current Paths (Continued)
sections are those in series with the main inductor,because it is known that inductors have the property of preventing sudden changes in current(this is analogous to a capacitor which‘resists’sudden changes in voltage).
Summing up:In switching regulator layout,it is the AC paths that are considered critical,whereas the
DC paths are not.That is the only basic rule to be kept in mind, and from which all the others follow.This is also true for any topology.Perform an analysis of the current flow for any topology in the same manner as we did for the Buck,to find the’difference traces’:and these traces are by defintion the’critical’ones for layout.
What is the problem with step current changes anyway?In a resistor for example,this causes no unexpected/ unidentifiable problem.The voltage is given by V=IR,and so for a given change of current,the voltage will change pro-portionally.For example,a0.5cm wide Cu trace of thick-ness1.4mil has a resistance of1milliohm per cm length (at20degC).So it seems that a1inch long trace with a current changeover of1A,would produce a change in volt-age of only2.5millivolts across the trace,which is insignifi-cant enough to cause the control sections of most ICs to misbehave.But in fact the induced voltage is much larger. The important thing to realize is that traces of copper on a PCB,though barely resistive,are also inductive.Now,the oft-repeated thumb-rule is that‘every inch of trace length has an inductance of about20nH’.Like the trace resis-tance,that too doesn’t seem much at first sight.But it is this rather minute inductance which is in fact responsible for a great many customer calls in SIMPLE SWITCHER applica-tions!
The equation for voltage across an inductance is V=L*dl/dt, and so the voltage does not depend on t
he current but on the rate of change of the current.This fact makes all the differ-ence when the1A change we spoke about occurs within a very short time.The induced voltage can be very high,even for small inductances and currents,if the dl/dt is high.A high dl/dt event occurs during transition from Figure1a to Figure 1b(and back)in all the AC trace sections(shown bold in Figure1c).The induced voltage spike appears across each affected trace,lasting for the duration of the crossover.
To get a better feel for the numbers here:the change in current in the AC sections of a typical buck converter is about 1.2times the load current during the switch turn-off transition and is about0.8times the load current during the switch turn-on transition(for an’optimally’designed Buck inductor,as per inductor design guidelines in the relevant Datasheets/Selection Software).The transition time is about30ns for high speed Fet switchers like the LM267x,and is about75ns for the slower bipolar switchers like the LM259x series.This also incidentally means that the voltage spikes in the high-speed families can be more than twice that in the slower families,for a comparable layout and load.Therefore layout becomes all the more critical in high-speed switchers.
So,one inch of trace switching say1A of instantaneous current in a transition time of30ns gives0.7V,as compared to 2.5mV(that we estimated on the basis of resistance alone).For3A,and two inches of trace,the induced voltage ’tries’to be4V!In Figure1c,the small triangles along the sections in
dicate the direction of the momentary induced voltage,as the converter changes from the situation in Fig-ure1a to that in Figure1b(switch turn-off).We can see that
assuming that the ground pin of the IC is the reference point,
the switching node(marked‘SW’)tries to go negative(all its
series trace sections adding up).Similarly the input pin
(marked‘VIN’goes high through series contributions in all its
related sections.Figure1c represents the picture during the
turn-off transition.During the turn-on transition all the in-
突变体duced voltage polarities shown are simply reversed.In that
case,the VIN pin is dragged low,and the switching node pin
is dragged high momentarily.
The astute designer will recognize that this was to be ex-
pected since any inductance,even if it is parasitic,demands
to be‘reset’,which means that the volt-seconds during the
on-time must equal and be opposite in sign to the
volt-seconds during the off-time.The designer will also real-
ize that till these parasitic trace inductances reset,they do
not’allow’the crossover to occur.So for example,traces
which were carrying current prior to switch turn-off will’insist’
on carrying current till the voltage spikes force them to do
otherwise.Similarly,the traces which need to start carrying
current will’refuse’to do so till the spikes across them force
them to do likewise.Since switching losses are proportional
to crossover time,even if these voltage spikes do not cause
anomalous behavior,they can degrade efficiency.For ex-
ample,in transformer-based flyback regulators,when the the
primary number of turns is much larger than the secondary
turns,designers may be surprised to learn how much the
secondary side trace inductances alone can degrade effi-
ciency.This is because any secondary side uncoupled
(trace/transformer leakage)inductances reflect into the
primary side as an equivalent parasitic inductance in
series with the switch.This adds an additional term to
the effective leakage as seen by the switch that equals
the secondary inductance multiplied by square of the
turns ratio(turns ratio being Np/Ns).Therefore the dissipa-
tion in the flyback clamp(zener/RCD)can increase dramati-
cally,lowering efficiency.One lesson here is that though
’leakage inductance’(from traces or the transformer)is con-
sidered’uncoupled’,in reality it can make its presence se-
verely felt from one side of the transformer to the other.So it
is not totally’uncoupled’at all!In fact this happens to be the
main reason why flybacks with low output voltages(high
turns ratio)show poorer efficiency as compared to higher
output flybacks.Therefore,reducing critical trace induc-
tances is important for several reasons:efficiency,EMI,be-
sides basic functionality.
The momentary voltage spikes which last for the duration of
the transition can be very hard to capture on an oscilloscope.
But they may be presumed to be present if the IC is seen to
be misbehaving for no’obvious reason’.These spikes,if
present with sufficiently high amplitude,can propagate into
the control sections of the IC causing what we call here a
controller’upset’.This leads to the observed performance
anomalies,and in rare cases this can even cause device
failure.Since none of these spike-related problems can be
easily corrected,or band-aided,once the layout is initially
bad,the important thing is to get the layout‘right’to start
with.
The designer may well ask,why is it that these step current
changes are a problem with the parasitic trace inductances,
and not with the main inductor of the Buck converter?That is
because all inductors try to resist any sudden current
change.But since the main inductor has a much larger
inductance(and energy storage)as compared to the para-
sitic trace inductances,it therefore ends up‘dominating’.
From V*dt=L*dl we can also see that if L is large,a much
higher voltseconds(V*dt)is required to cause a given
AN-1229
www.national
3
The AC and DC Current Paths
(Continued)
change in current.The trace inductances therefore simply ’give in’first before the main inductor does.But they certainly don’t go down without and the voltage spikes bear testimony to this!
Notice that the currents in the signal traces in the schematic are not shown.For example those connected to the com-pensation node (marked ‘COMP’)or bootstrap (marked ‘BOOST’)carry relatively minute currents and therefore are not likely to cause upsets.They are therefore not critical and can be routed relatively ‘carelessly’.The feedback trace is an exception,and will be discussed later.The Ground pin of the IC is another potential entry point of noise pickup.Inex-perienced designe
rs often grossly under estimate the needs of this pin,particulary for Buck converters.They assume that since the main power flow in a Buck converter does not pass through the ground pin,the ‘current through the ground pin is very low’,and therefore the trace length leading up to this pin is not critical.In fact,though the average current through this pin is very low,the peak current or its dl/dt is not.Consider the switch driver as shown schematically in Figure 1.Clearly it needs to supply current to drive the switch.In any Fet operated as a switch,large peak to peak instantaneous current spikes are needed to charge and discharge the gate capacitance.This is essential so as to cause the Fet to switch fast,and this reduces the switching/crossover losses inside the switch and improves the overall efficiency of the converter.(Actually,in a practical IC,the ‘spike’of current comes from the bootstrap capacitor,and then the bootstrap capacitor is quickly refreshed by the internal circuitry of the IC ----it is the refresh current that passes through the ground pin).Further,as in any high-speed digital IC,parts of the internal circuitry,clocks,gates,comparators etc.,can turn on and off suddenly,leading to small but abrupt changes in the current through the ground pin.This can cause ’ground bounce’which in turn can lead to controller upsets.There-fore the length of the trace to the Ground pin also needs to be kept as small as possible.This also implies that the input capacitors,especially the bypass capacitor ‘CBYPASS’should be placed very close to the IC ,even for a Buck IC.
Placing Components ‘acap’(as Close as Possible)
One has heard this before:“component X needs to be ‘acap’”.Soon we are told the “component Y too needs to be ‘acap’”.Then “Z too”.And so on.Which would be physically impossible because matter cannot occupy the same place at the same time!So which one comes first?This is the million-dollar predicament always facing switcher layout.
The troubling trace lengths are those indicated Figure 1c .To keep them small,clearly two components need to be acap.These are the input bypass capacitor and also the catch diode.Consider the input capacitor section first.
微计算机信息In the schematic there are in two input capacitors shown.These are marked ‘CIN’and ‘CBYPASS’respectively.The purpose of the total input capacitance is to reduce the volt-age variations at the input pin.The variations are mainly due to the pulsed input current waveshape,as demanded by a Buck topology.Note that for this particular topology,the output capacitor current is smooth (because the inductor is in series with it).In a Boost topology the situation is he input capacitor current is smooth and the current into the output capacitor is pulsed.This makes the
demand for input decoupling less stringent than in a Buck (or Buck-Boost).In a Buck-Boost or ’flybac
k’,both the input and the output capacitor currents are pulsed,and input decou-pling is required not only for the control-section/drivers of the IC but for the input current step waveform of the power stage.Designers familiar with a Cuk topology know that in this case both input and output currents are smooth.The Cuk converter is therefore often called the ’ideal DC to DC’converter,and expectedly its parasitic inductances can be largely ignored ----because there are no AC trace sections in the sense we described.
Now if the input power to a Buck converter was coming through long leads from a distant voltage source,the induc-tance of the incoming leads would seriously inhibit their ability to provide the fast changing pulsed current shape.So an on-board source of power is required right next to the converter,and this is provided by the input capacitor.It provides the pulsed current,and then is itself refreshed at a slower rate (DC current)from the distant voltage source.However,since the input capacitor is fairly large in size,it may not be physically possible to place it as close as de-sired.Especially for very high speed switchers such as the LM267x series (note that a ‘high speed’switcher as de-fined here,is one with a very small crossover/transition time,and it does not necessarily have to be one with a high switching frequency ).In addition,the Equivalent Se-ries Resistance (‘esr’)and Equivalent Series Inductance (‘esl’)of the main input capacitor may be too high,
and this can cause high frequency input voltage ripple on the VIN pin.For the Buck converter schematic as shown in Figure 1,the input pin connects not only to the Drain of the Fet switch,but also provides a low internally regulated supply rail to the control sections of the IC.But no real series pass regulator can ’hold off’very fast changes in the applied input voltage.Some noise will feed through into the control section and then much will depend on the internal sensitivity of the IC to noise (related to its design,internal layout,process/logic family).It is therefore best to try to keep voltage on the VIN pin fairly clean --—from a high frequency point of view.Note that it is not being suggested here that one responds to this statement by increasing the input capacitance indiscrimi-nately,because we are not talking about the natural input voltage ripple which occurs at the rate of the switching frequency (e.g.100kHz–260kHz).Our concern here is the noise occurring at the moment of the transitions,and this noise spectrum peaks at around 10MHz–30MHz,as deter-mined by the transition/crossover time of the switch.The crossover time has nothing to do with the basic PWM switch-ing frequency,but does ofcourse depend on the type of switch bipolar or Fet.
Therefore a high frequency ‘bypass’or ‘decoupling’capacitor with small or no leads,shown as ‘CBYPASS’in Figure 1,is to be placed very close to the VIN and GND pins of the IC.This is usually a 0.1µF–0.47µF (monolithic)multilayer ceramic (typically X7R type,size 1206or the more recent ’invert
ed’termination version of this popular size,the ’0612’----also note that smaller sized ceramic caps generally have higher esr/esl,but check before use).Since now this com-ponent provides the main pulsed current waveshape,the bulk capacitor shown as ‘CIN’,may be moved slightly further up (about an inch)without any deleterious effect.For lighter loads,and if it is possible to place the input bulk capacitor very close to the IC,the high frequency bypass capacitor may sometimes be omitted.But for high-speed switchers like the LM267x,the input ceramic bypass capacitor is considered almost mandatory for any application.
A N -1229
www.national
4
Placing Components‘acap’(as Close as Possible)(Continued)
The position of the catch diode is also critical.It too needs to be acap.Now,every topology has a node called the’switch-ing node’.This is the’hot’or’swinging’end of the switch.For integrated switchers,this node can also be an easy entry point for noise feed-through into the control sections.Note that the pr
oblem is not caused by the simple fact that the voltage at this node swings,for it is designed for exactly that situation in mind.The problem is with the additional noise spikes riding on top of the basic square voltage waveform, arising from the trace inductances as explained earlier. Therefore,it is essential to place the catch diode very close to the IC and connect it directly to the SW pin and GND pins of the IC,with traces that are very short and fairly wide.In some erroneous layouts,where the catch diode was not appropriately placed to start with,the con-verter could be‘bandaided’by a small series RC snubber. This consists typically of a resistor(low inductive type preferred)of value10Ω–100Ωand a capacitor,which should be ceramic of value470pF–2.2nF.Larger capaci-tance than this would lead to unacceptably higher dissipation (=1/2*C*V2*f),chiefly in the resistor,and would serve no additional purpose.However,note that this RC snubber needs to be placed very close to and across the Switch-ing pin and Gnd pin of the IC,with short leads/traces. Sometimes designers think that this is’across the diode’, because on the schematic there is no way to tell the differ-
ence.However,particularly when the diode is a Schottky,the
primary purpose of such a snubber is to absorb the voltage
spikes of the trace inductances.Therefore its position must
be such that it provides bypassing of the critical or AC trace
sections of the output side as shown in Figure1c(right hand
side of the switcher)----which means it must be close to the
IC.Of course,as mentioned previously,it is best to get the
layout right to start with,rather than adding such extra
法components.
Remaining component placements can be taken up only
after the input bypass capacitor and the catch diode are
firmly in place and are both acap.The traces to either of
these two components should be short,fairy wide,and
should not go pass through any vias on the way to the IC.
For SMT boards this implies that the input capacitor and
catch diode are on the same layer as the IC.In Figure2
suggested PCB starting points are provided for several
switchers.All of them focus on placing these two critical
components correctly.These layouts are strongly recom-
mended for most applications.The’X’marks suggest the
recommended location where vias can be used to con-
nect to a Ground Plane(if present).The remaining compo-
nents can be placed relatively carelessly(though in doing so,
there may be slight impact,for example on the accuracy of
王庸晋the output voltage rail and its ripple,but nothing compared to
what can happen if the input decoupling cap and catch diode
are incorrectly placed).Trace routing is now discussed in
more detail.
AN-1229
www.national
5
豫公网安备41160202000603
站长QQ:729038198
关于我们
投诉建议