摘要
随着嵌入式系统、便携式设备的大量涌现，功耗问题已越来越被人们所关注。甚至在电路设计中成了主要的约束。在自顶向下设计的每个层次上，设计者都需要经过一个功耗评估，优化调整的循环过程。低层的（电路级，门级）功耗评估工具虽然有较高的精度，但是仿真速度太慢，不适合目前庞大复杂的系统。因此需要一个快速，精确的功耗评估机制。 本文的研究背景是为面向低功耗的SoC系统设计中的体系结构优化和软件（编译器）优化提供支持。从这个角度出发，本文提出了一种包含指令级功耗模型和部件级功耗模型在内的两层系统级功耗模型。 霍普
部件级功耗模型是系统级功耗模型的基础，它根据部件的结构信息，自底向上的计算各个部件的功耗。存储系统的能耗分成两部分：指令/数据cache和主存部分使用分析模型；指令/数据cache和数据通路间的总线使用翻转敏感模型。对于数据通路中的部件采用周期精确的输入翻转敏感功耗模型。并根据位操作，将部件分为位无关部件和位相关部件。位无关功能部件的每个比特位的变化是独立的，不受其它比特位变化的影响，也不影响其它比特位的变化。位相关功能部件的各个比特位的变化是相关联的，某个比特位的变化会影响其它比特位具体符合说
的操作或某个比特位的变化会受到其它比特位的影响。根据两类部件结构的特点，采用不同的方法建立功耗模型。
指令级功耗模型包括指令的静态功耗和指令间的动态功耗。每条指令的执行会涉及到数据通路上的一系列相关部件，并引起这些部件的开关活动。不同的操作码和寻址方式以及地址和数据的编码方式，确定了每条指令的基本功耗。在程序动态执行过程中，由于执行上下文的切换，会带来额外的附加功耗，这部分功耗称为动态功耗。对指令功耗的分析，最终可转化为对周期功耗的分析。
本文提出的系统级两层功耗模型是周期精确的。在微结构层结合了统计分析和翻转敏感两种模型, 由于考虑了功耗中的数据依赖性，因此可以得到比较精确的、能用于指导体系结构层的优化的功耗评估结果。同时在微结构层的基础上，本文建立了指令级功耗模型，可以有效的支持编译器的优化工作。
关键词：功耗评估 系统级功耗模型 部件级功耗模型 指令级功耗模型 翻转敏感
*本文工作得到国家自然科学基金（No.60273042）项目和安徽省自然科学基金（No.03042101）项目的支持，在此表示感谢。
独眼喙鼻
Abstract
With the emergence of embedded systems and portable applications, power consumption has become a hot issue, which considered a major design constraint. Designers must be concerned with both estimating and optimizing the energy dissipation at every level of the top-down design hierarchy. Power estimation at the lower levels is high accurate, but difficult and expensive to the growing complexity system. Efficient and accurate power estimation technique becomes indispensable.
To support architectural level optimization and software optimization in low power SoC architecture design, a cycle accurate system level power model is purposed, which consists of instruction level model and microarchitecture model.
The microarchitecture model is the base of system level power model. The technique proposed in this paper is a bottom-up approach that relies on extracting a power model fr
om an existing circuit and utilizes the structural information. Storage system is divided into instruction/data cache and memory, which are modeled with analytical method, and buses between instruction/data cache and datapath, which are modeled with transition sensitive method. According to operation of bit, units can be divided into bit-independent units and bit-dependent units. In a bit-independent unit, the operation in one bit slice does not depend on and affect the values of other bit slices. Contrarily, in a bit-dependent unit, the operation in one bit slice depends on or affects other bit slices. These two class units are modeled with different methods.
半夏种植
Instruction level power model consists of static energy cost and dynamic energy cost. Each instruction activates some units. The static energy cost of an instruction due to operand and address values. During the execution of a program, additional energy costs occur due to context switch, witch named dynamic energy cost. The analysis of instruction level power can be converted to analyze cycle-accurate power.
The system-level power model is cycle-accurate, which combines analytical model and tr
ansition-sensitive model. Since our technology involves data dependent on microarchitecture, it possible to get accurate power estimation, which can be used in low power architectural optimization. This paper also proposes an instruction level model which supports low power compiling optimization.
Keywords: power estimation, system level power model, function level power model, instruction level吸收犯 power model, transition-sensitive
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