Features
•Advanced, High-speed, Electrically-erasable Programmable Logic Device
–Superset of 22V10
–Enhanced Logic Flexibility
–Backward Compatible with ATV750B/BL and ATV750/L
•Low-power Edge-sensing “L ” Option with 1 mA Standby Current •D- or T -type Flip-flop
•Product Term or Direct Input Pin Clocking for Flip-flop •7.5 ns Maximum Pin-to-pin Delay with 5V Operation
•
Highest Density Programmable Logic Available in 24-pin and 28-pin Packages –Advanced Electrically-erasable Technology –Reprogrammable –100% Tested
•Increased Logic Flexibility
–42 Array Inputs, 20 Sum Terms and 20 Flip-flops •Enhanced Output Logic Flexibility
–All 20 Flip-flops Feed Back Internally
–10 Flip-flops are also Available as Outputs •Programmable Pin-keeper Circuits
•Dual-in-line and Surface Mount Package in Standard Pinouts •Full Military, Commercial and Industrial Temperature Ranges •20-year Data Retention •2000V ESD Protection •1000 Erase/Write Cycles
•
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Block Diagram
Note:
For PLCC, pins 1, 8, 15, and 22can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.
Pin Configurations
Pin Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC
+5V Supply
DIP/SOIC/TSSOP
PLCC/LCC
2
ATF750C(L)
0776K–PLD–07/07
Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform predictable delays guar-antee fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology.
Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually config-urable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, pro-viding added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily imple-mented with logic to spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking.Each output has its o
wn enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.
The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL pro-vides the optimum low-power CPLD solution. This device significantly reduces total system power, thereby allowing battery-powered operations.
DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to be either 2.7V to 3.6V , 5V ±5% or 5V ±10%.
Absolute Maximum Ratings*
T emperature -55°C to +125°C *NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exp
osure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1.Minimum voltage is -0.6V DC, which may under-shoot to -
2.0V for pulses of less than 20 ns.Maximum output pin voltage is V CC + 0.75V DC,which may overshoot to 7.0V for pulses of less than 20 ns.
Storage .-65°C to +150°C Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V (1)Voltage on Input Pins with Respect to Ground
.-2.0V to +14.0V (1)Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V (1)
5V Operation
Commercial -7.5, -10, -15Industrial -10, -15Military Operating T emperature (Ambient)0°C - 70°C -40
°C - +85°C -55°C - +125°C
(case)V CC Power Supply
5V ± 5%
5V ± 10%
5V ± 10%
3
ATF750C(L)
0776K–PLD–07/07
Logic Options
Clock Mux
在
网络暴力中捍卫自己
Output Options
dmx512协议Combinatorial Output
Registered Output
4
ATF750C(L)
0776K–PLD–07/07
Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic co
mpiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.
Input Diagram
I/O Diagram
5
ATF750C(L)
0776K–PLD–07/07
Note:
1.Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and Measurement Levels
t R , t F < 3 ns (10% to 90%)
Output Test Load
DC Characteristics
Symbol Parameter Condition
Min
Typ
Max Units I LI Input Load Current V IN = -0.1V to V CC + 1V 10µA I LO
Output Leakage Current
V OUT = -0.1V to V CC + 0.1V
10µA I CC
Power Supply Current, Standby
V CC = Max,V
IN = Max,Outputs Open
C-7, -10
Com.125
180mA Ind., Mil.135190mA C-15
Com.125180mA Ind., Mil.135190mA CL-15
Com.0.121mA Ind.
0.15
2mA I OS (1)Output Short Circuit Current V OUT = 0.5V -120
mA V IL Input Low Voltage 4.5 ≤ V CC ≤ 5.5V
-0.60.8V V IH
Input High Voltage
2.0
V CC + 0.75
V V OL
蒲剧苏三
起解Output Low Voltage V IN = V IH or V IL ,V CC = Min I OL = 16 mA
Com., Ind.0.5V I OL = 12 mA Mil.0.5V I OL = 24 mA
Com.
0.8
长城客户管理系统
V V OH Output High Voltage
V IN = V IH or V IL ,V CC = Min
I OH = -4.0 mA
2.4
V
6
ATF750C(L)
0776K–PLD–07/07珍妃之印
AC Waveforms, Product Term Clock (1)
Note: 1.Timing measurement reference is 1.5V . Input AC driving levels are 0.0V and 3.0V , unless otherwise specified.
Note:
1.See ordering information for valid part numbers.
AC Characteristics, Product Term Clock (1)
Symbol
Parameter
-7
-10
C/CL-15Units Min
Max Min
Max Min
Max t PD Input or Feedback to Non-registered Output 7.51015ns t EA Input to Output Enable 7.51015ns t ER Input to Output Disable 7.5
10
15
ns t CO Clock to Output 37.5410512ns t CF Clock to Feedback 15
47.5
59
ns t S Input Setup Time 348/12ns t SF Feedback Setup Time 347ns t H Hold Time 125ns t P Clock Period 71114ns t W
Clock Width
3.5
5.5
7
ns f MAX External Feedback 1/(t S + t CO )
957150/41MHz Internal Feedback 1/(t SF + t CF )1258662MHz No Feedback 1/(t P )
142
90
71
现代中西医结合杂志MHz t AW Asynchronous Reset Width 51015ns t AR Asynchronous Reset Recovery Time
3
10
15
ns t AP Asynchronous Reset to Registered Output Reset 8
12
15
ns t SP Setup Time, Synchronous Preset
4
7
8
ns
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