克痢痧Hi3516A Professional HD IP Camera SoC Brief Data Sheet
Issue 03
Date 2014-10-10
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Key Specifications Processor Core
z A7@600 MHz, 32 KB I-cache, 32 KB D-cache/128 KB L2 cache
z Neon acceleration, integrated FPU
Video Encoding
z H.264 BP/MP/HP
z H.265 main profile
z MJPEG/JPEG baseline encoding
Video Encoding Performance z A maximum of 5-megapixel resolution for H.264/H.265 encoding
教育
评价z Real-time H.264/H.265 encoding of multiple streams: −1080p@30 fps+720p@30 fps+VGA@30 fps
−1080p@60 fps+VGA@30 fps
−5-megapixel@30 fps+VGA@30 fps
z JPEG snapshot at 5-megapixel@8 fps
z Supporting the CBR/VBR bit rate control mode, ranging from 16 kbit/s to 40 Mbit/s
z Encoding frame rate ranging from 1/16 fps to 240 fps
z Encoding of eight ROIs
Intelligent Video Analysis
z Integrated IVE, supporting various intelligent analysis applications such as motion detection, boundary security and video diagnosis
Video and Graphics Processing z3D denoising, image enhancement, and dynamic contrast enhancement
z Anti-flicker for output videos and graphics
z1/15.99x to 16x video scaling
z1/2x to 2x graphics scaling
z OSD overlay pre-processing for eight regions
z Video graphics overlaying of two layers (video layer and graphics layer)
ISP
z Adjustable 3A functions (AE, AWB, and AF)
z Noise reduction in FPN mode
z Highlight compensation, backlight compensation, gamma correction, and color enhancement
z Defect pixel correction, denoising, and digital image stabilizer
z Anti-fog
z Lens distortion correction
石油信息
z Picture rotation by 90° or 270°
z Mirroring and flipping
z Digital WDR, frame base/line base WDR, and tone mapping z ISP tuning tools for the PC
Audio Encoding/Decoding
z Voice encoding/decoding in compliance with multiple protocols by using software
z G.711, ADPCM, and G.726 protocols
z AEC, ANR, and ALC
Security Engine
z Various encryption and decryption algorithms using hardware, such as AES, DES, and 3DES
z Digital watermark
Video Interfaces
z Input
−8-/10-/12-/14-bit RGB Bayer DC timing VI, a
maximum of 150 MHz clock frequency
−BT.601, BT.656 or BT.1120 VI interface
−MIPI, LVDS/sub-LVDS, and HiSPI
−Compatibility with mainstream HD CMOS sensors
provided by Sony, Aptina, OmniVision, and Panasonic −Compatibility with the electrical specifications of
parallel and differential interfaces of various sensors
−Programmable sensor clock output
−Maximum input resolution of 5 megapixels
z Output
−One PAL/NTSC output for automatic load detection
−One BT.1120/BT.656 VO interface for connecting to
an external HDMI or SDI, up to 1080p@60 fps output Audio Interfaces
z Integrated audio CODEC, supporting 16-bit audio inputs and outputs
z I2S interface for connecting to an external audio CODEC Peripheral Interfaces
z POR
z One integrated high-precision RTC
z One dual-channel SAR ADC
z Four UART interfaces
z One IR interface, three I2C interfaces, four SPI master interfaces, 14 x 8 + 3 GPIO interfaces
z Eight PWM interfaces (four independent interfaces and four multiplexed with other pins)
z Two SDIO 3.0 interfaces, supporting SDXC
z One USB 2.0 host/device port
z RGMII/RMII/MII in 100/1000 Mbit/s full-duplex or half-duplex mode, PHY clock output, and TSO network
acceleration
External Memory Interfaces
z DDR3/3L SDRAM interface
−One 32-bit DDR3/3L interface with the maximum银行钱荒的影响
frequency of 600 MHz (1.2 Gbit/s)
−Maximum capacity of 4 Gbits for a 16-bit DDR
−Maximum capacity of 8 Gbits for two 16-bit DDRs
z SPI NOR flash interface
−1-, 2-, or 4-wire mode
−Maximum capacity of 32 MB
z SPI NAND flash interface
−Maximum capacity of 4 Gbits
z NAND flash interface
−8-bit data width
−SLC or MLC
−4-, 8-, or 24-bit ECC
−Components with 8 GB capacity or larger
z Booting from the SPI NOR flash, SPI Nand Flash or NAND flash
SDK
z Linux-3.4-based SDK
z High-performance H.264/H.265 PC decoding library Physical Specifications
z Power consumption
− 1.1 typical power consumption@1080p60
−Multi-level power-saving mode
z Operating voltages
− 1.1 V core voltage
− 3.3 V I/O voltage and 3.8 V margin voltage
− 1.35 V or 1.5 V DDR3/3L SDRAM interface voltage z Package
−Body size of 15 mm x 15 mm (0.59 in. x 0.59 in.), 0.65
mm (0.03 in.) ball pitch, TFBGA RoHS
Functional Block Diagram
As a new-generation SoC designed for the HD IP camera, the Hi3516A integrates a new-generation
ISP and adopts the latest H.265 compressed video encoder, advanced low-power technology, and low-power architecture design. These features help the Hi3516A keep the leading position in the aspects of low bit rate, high picture quality, and low power consumption. The Hi3516A supports 90° or 270° rotation and lens distortion correction, which meets requirements in various surveillance applications. It also fully supports 3A algorithms, which allow customers to design different types of IP cameras including the IP AF zoom module. The Hi3516A integrates the POR, RTC, and audio CODEC and supports various sensor levels and clock outputs, which significantly reduces the EBOM costs for the Hi3516A HD IP camera. Similar to other HiSilicon DVR and NVR SDKs, the Hi3516A SDK features high stability and ease of use, which allows rapid mass production and facilitates system layout of IP cameras, DVRs, and NVRs.
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