摘 要
随着集成电路的规模和复杂度不断增大，验证的作用越来越重要。要在较短的时间内保证芯片最终能正常工作，需要将各种验证方法相结合，全面充分地验证整个系统。
FF-DX是一款高性能定点DSP，为了在提升芯片性能的同时，缩短设计周期，降低开发成本，
采用了半定制/全定制混合设计的方法，对RTL级代码进行优化改进，对处理器内核的执行单元采用全定制设计实现。混合设计的复杂性，给验证工作带来了巨大的挑战。本文针对半定制/全定制混合设计的特点，提出并实现了一套半定制/全定制混合设计流程中功能和时序验证的方法。
城轨论文从模拟验证、等价性验证和全定制设计的功能验证三个方面对FF-DX的分支控制部件进行功能验证。对于模拟验证中激励的产生，采用了手工生成和伪随机生成相结合的方法，并通过覆盖率评估，使设计的代码覆盖率达到98%。对于全定制模块，采用了NC-Verilog模拟器和功能模型提取工具TranSpirit相结合的新方法，提高了验证效率。论文还研究了运用形式验证的方法对RTL级和RTL级以及RTL级和门级网表进行等价性验证。为了进一步保证RTL级设计和对应的全定制设计模块之间功能的等价性，设计了一个能同时考察两种设计的验证平台，以此来提高工作效率。
论文介绍了FF-DX地址计算部件的时序建模和静态时序分析方法。在静态时序分析之后，将SDF文件中的延时信息反标到逻辑网表中，通过动态时序验证进一步保证设计的时序收敛。
论文还结合工程任务，设计实现了验证过程中使用的几种辅助工具，大大提高了验证的效率，减少了人工参与带来的失误。
运用上述验证方法对FF-DX功能部件进行验证，取得了较好的效果，缩短了验证周期，提高了验证效率。
主题词：半定制/全定制混合设计，功能验证，形式验证，n 二甲基亚硝胺时序验证，时序模型，静态时序分析，辅助工具
ABSTRACT
The complexity and size of the modern VLSI has been increasing dramatically, which present a significant challenge for verification. In order to ensure proper function of the design, various methods need to be used to verify the entire system sufficiently.
FF-DX, a high-performance fix-point DSP our group designed, has adopted several design methods to enhance performance, as well as cut down design cycle and lower the
cost. The most featured one is what we called blended methodology which mixes semi-custom and full-custom design methods together. Nevertheless, this methodology has led to a huge challenge to verification because of the complexity it brings in. In this dissertation, based on the characteristics of the blended methodology, we propose a flow for functional and timing verification, with the novel idea of combining full-custom and semi-custom verification methods.
We verify the branch control function unit in three aspects, simulation verification, equivalence verification, together with functional verification in the full-custom designs. A blended methodology is introduced to generate the testbench for functional verification, which combines both manual and pseudo-random methods, and after evaluation, the code coverage rate is 98%. We also adopt a new methodology of combining the NC-Verilog simulator with functional model extractor TranSpirit for full-custom block ,and it speed up verification efficiency. Besides, we studied equivalence verification, a formal verification methodology which is used for RTL-RTL and RTL-gate design. To guarantee t
he functional equivalence between RTL design and full-custom design further, we design a testbench which can verify the two designs at the same time and it can greatly improve efficiency.
This paper introduces a methodology of timing modeling and STA in FF-DX core. After STA, we backanotate the delay info into the logical netlist, then the timing closure could be assured further by another dynamic timing analysis.
To meet the requirement of out project, we design several tools which are used in verification. These tools greatly enhance the efficiency of verification, as well as reduce the man-made errors.
We use the above methods to finish verification of the core module of FF-DX, which effectively shorten design cycle, and speed up verification efficiency.
Key Words：Semi-custom/Full-custom Mixed Design, Functional Verification, Formal Verification, Timing Verification, Timing Model, Static Timing Analysis, Aiding Tool
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