DDR Interface Design Implementation
括约肌A Lattice Semiconductor White Paper
December 2004
Lattice Semiconductor
5555 Northeast Moore Ct.
Hillsboro, Oregon 97124 USA
Telephone: (503) 268-8000金熙俊
www.latticesemi
Memory Overview
Over the past several years the electronics market and, more specifically, the memory market has undergone significant change. Prior to the electronics industry downturn in 2000, electronic system designers were less concerned with the cost of the components going into their next design, and more concerned with the raw, maximum performance they could achieve.
Today, increasing competition and decreasing profit margins have forced system designers to reduce next generation product cost while maintaining, or even increasing, system performance. One industry segment that has experienced substantial growth as a result of this transition is DRAM memory, particularly Double Data Rate (DDR) SDRAM memory.
DDR Memory first came on the scene as a high performance, low-cost memory solution targeted primarily at the personal computer and other cost sensitive consumer markets. More recently, due to the economic pressures squeezing the entire electronics industry, non-consumer products have also begun to incorporate DDR memory (Figure 1).
DDR is an evolutionary memory technology based on SDRAM. DDR SDRAM access is twice as fast as SDRAM, because DDR data transfers occur on both edges of the clock, compared to SDRA
范立础M, which transfers data only on the rising edge of a clock. Consequently, DDR can transfer data at up to 2133MB/s. DDR also consumes much less power than conventional SDRAM, with an operational Vcc of just 2.5Vdc instead of 3.3Vdc for SDRAM.
Market analyses indicate that DDR is currently utilized in over 50% of all electronic systems, and usa
ge is expected to increase to 80% over the next several years. DDR is not, and will never be, an “all things to all designs”technology. DDR memory is well suited for those designs that have a high read to write ratio. Quad Data Rate memory, for example, is designed for applications that require a 50% read/write ratio. Figure 2 identifies various state of the art memory technologies and where on the read/write curve they reside.
Figure 2: Read/Write Ratio Comparison of Various Memory Types
As noted, each system has its own unique memory requirements. In the case of server applications, the READ-to-WRITE ratio tends to be high, indicating a need for DDR. In the case of a network processor interfacing a MAC supporting jumbo packets, where the packets need to be buffered and stored before being processed, a near equal 1:1 READ-to-WRITE ratio exists, indicating QDR as a more appropriate memory architecture.
Figure 3 highlights a generic communications line card Printed Circuit Board (PCB) example. The block diagram shows where several common memory types may be utilized, based on the system designer’s requirements. A similar decision process is used in a wide variety of systems in order to choose the
appropriate memory architecture.
电子设计技术
Figure 3: Utilization of Common Memory Types
The following list indicates the appropriate memory architecture for a variety of systems and functions. These selections are based on the system architecture and the respective performance/cost trade off requirements.
•Lookup - Fast Switching/Access time
–Latency Critical, Read Oriented, Smaller Bus Width (32/64bit)
–Memory Choice: ZBT (<10Gb/s) -> QDR/DDR (>10Gb/s)
–Operation: Address Translatio n
•Lookup - Large Size, High Throughput (Core Router)
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