1.General description
The PCA9674/74A provide general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional bus (I 2C-bus) and is a part of the Fast-mode Plus (Fm+) family.
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The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-mode Plus I 2C-bus speeds (1MHz versus 400kHz) so that the output can support PWM
dimming of LEDs, higher I 2C-bus drive (30mA versus 3mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (200mA versus 100mA) that supports having all LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts.
The devices consist of an 8-bit quasi-bidirectional port and an I 2C-bus interface. The
PCA9674/74A have low current consumption and include latched outputs with 25mA high current drive capability for directly driving LEDs.
They also possess an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I 2C-bus.
The internal Power-On Reset (POR) or Software Reset sequence initializes the I/Os as inputs.
2.Features
I 1MHz I 2C-bus interface
I Compliant with the I 2C-bus Fast and Standard modes I SDA with 30mA sink capability for 4000pF buses I 2.3V to 5.5V operation with 5.5V tolerant I/Os
I 8-bit remote I/O pins that default to inputs at power-up
I Latched outputs with 25mA sink capability for directly driving LEDs I T otal package sink capability of 200mA I Active LOW open-drain interrupt output
I 64 programmable slave addresses using 3 address pins
I Readable device ID (manufacturer, device type, and revision)I Low standby current
I −40°C to +85°C operation
I
ESD protection exceeds 2000V HBM per JESD22-A114, 200V MM per JESD22-A115, and 1000V CDM per JESD22-C101
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I 2C-bus with interrupt
Rev. 02 — 12 October 2006
Product data sheet
I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
I Packages offered: DIP16, SO16, SSOP20, TSSOP16, HVQFN16
3.Applications
I LED signs and displays
I Servers
I Industrial control
I Medical equipment
I PLCs
I Cellular telephones
I Gaming machines
I Instrumentation and test measurement
4.Ordering information
Table 1.Ordering information
Type number Topside
mark Package
Name Description Version
PCA9674BS9674HVQFN16plastic thermal enhanced very thin quadflat package;no leads;
16 terminals; body 3×3×0.85mm SOT758-1
PCA9674ABS674A
PCA9674D PCA9674D SO16plastic small outline package; 16 leads; body width 7.5mm SOT162-1 PCA9674AD PCA9674AD
PCA9674N PCA9674N DIP16plastic dual in-line package; 16 leads (300mil); long body SOT38-1 PCA9674AN PCA9674AN
PCA9674PW PCA9674TSSOP16plastic thin shrink small outline package; 16 leads;
body width4.4mm SOT403-1
PCA9674APW PA9674A
PCA9674TS PCA9674SSOP20plastic shrink small outline package; 20 leads;
body width4.4mm SOT266-1
PCA9674A TS PCA9674A
5.Block diagram
Fig 1.Block diagram of PCA9674/74A
Fig 2.Simplified schematic diagram of P0 to P7
002aac108
INT I 2C-BUS CONTROL
INTERRUPT LOGIC
PCA9674PCA9674A
LP FILTER
AD0AD1AD2INPUT FILTER
SHIFT REGISTER
SDA
SCL 8 BITS
write pulse read pulse
POWER-ON RESET
V DD V SS
I/O PORT
P0 to P7
002aac109
write pulse
read pulse
D CI S
FF Q
power-on reset
data from Shift Register
I trt(pu)
100 µA
I OH
I OL
V DD
P0 to P7
V SS
D CI S FF
Q
data to Shift Register
to interrupt logic
6.Pinning information
6.1Pinning
Fig 3.Pin configuration for SO16
Fig 4.Pin configuration for TSSOP16
Fig 5.Pin configuration for DIP16Fig 6.Pin configuration for SSOP20
Fig 7.Pin configuration for HVQFN16
PCA9674D PCA9674AD
AD0V DD AD1SDA AD2SCL
P0INT P1P7P2P6P3P5V SS
P4
002aac111
12345678
109
121114131615PCA9674PW PCA9674APW
AD0V DD AD1SDA AD2SCL
P0INT P1P7P2P6P3P5V SS
P4
002aac113
党史文苑
12345678
109
121114131615PCA9674N PCA9674AN
AD0V DD AD1SDA AD2SCL P0INT P1P7P2P6P3P5V SS
P4
002aac110
12345678
109
121114131615PCA9674TS PCA9674ATS
INT SDA P5
V DD P4AD0V AD2
P2P0P1
002aac112
123456789
10
12111413161518172019T ransparent top view
4
9
3102111125
6
7
8
16151413terminal 1index area
002aac114
PCA9674BS PCA9674ABS
P2
P6
P1P7P0INT AD2SCL P 3
V S S
P 4
P 5
A D 1
A D 0V D D
S D A
6.2Pin description
Table 2.Pin description for DIP16, SO16, TSSOP16
Symbol Pin Description
AD01address input 0
AD12address input 1
AD23address input 2
P04quasi-bidirectional I/O0
P15quasi-bidirectional I/O1
P26quasi-bidirectional I/O2
P37quasi-bidirectional I/O3
V SS8supply ground
P49quasi-bidirectional I/O4
P510quasi-bidirectional I/O5
P611quasi-bidirectional I/O6
P712quasi-bidirectional I/O7
INT13interrupt output (active LOW)
SCL14serial clock line
SDA15serial data line
V DD16supply voltage
Table 3.Pin description for SSOP20
Symbol Pin Description
INT1interrupt output (active LOW)
SCL2serial clock line
<3not connected
SDA4serial data line
V DD5supply voltage
AD06address input 0
AD17address input 1
<8not connected
AD29address input 2
土著菌
P010quasi-bidirectional I/O0
P111quasi-bidirectional I/O1
P212quasi-bidirectional I/O2
<13not connected
P314quasi-bidirectional I/O3
V SS15supply ground
P416quasi-bidirectional I/O4
P517quasi-bidirectional I/O5
为他人开一朵绚丽的花n.c.18not connected
P619quasi-bidirectional I/O6
P720quasi-bidirectional I/O7
Table 4.Pin description for HVQFN16
Symbol Pin Description
AD21address input 2
P02quasi-bidirectional I/O0
东乡论坛P13quasi-bidirectional I/O1 P24quasi-bidirectional I/O2
P35quasi-bidirectional I/O3
V SS[1]6supply ground
P47quasi-bidirectional I/O4
P58quasi-bidirectional I/O5
P69quasi-bidirectional I/O6
P710quasi-bidirectional I/O7
INT11interrupt output (active LOW)
SCL12serial clock line
SDA13serial data line
V DD14supply voltage
AD015address input 0
AD116address input 1
[1]HVQFN package die supply ground is connected to both the V SS pin and the exposed center pad.The V SS
pin must be connected to supply ground for proper device operation.For enhanced thermal,electrical,and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7.Functional description
Refer to Figure 1 “Block diagram of PCA9674/74A”.
7.1Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9674/74A is shown in Figure8. Slave address pins AD2, AD1, and AD0 choose 1 of
64slave addresses. T o conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 5 “PCA9674 address map” and T able 6 “PCA9674A address map”.
Remark:When using the PCA9674A, the General Call address (00000000b) and the
Device ID address (1111100Xb) are reserved and cannot be used as device address.
Failure to follow this requirement will cause the PCA9674A not to acknowledge.
Remark:When using the PCA9674or the PCA9674A,reserved I2C-bus addresses must
be used with caution since they can interfere with:
•“reserved for future use” I2C-bus addresses (0000011, 1111101, 1111110,
1111111)
•slave devices that use the 10-bit addressing scheme (11110xx)
•High speed mode (Hs-mode) master code (00001xx)
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