1
Features
•Low-voltage and Standard-voltage Operation, VCC = 2.7V–5.5V •Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K), or 2048 x 8 (16K)•Two-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol •400 kHz Compatibility
•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed
•Self-timed Write Cycle (5 ms max)•
High Reliability
–Endurance: One Million Write Cycles –Data Retention: 100 Years –ESD Protection: >3000V
Description
The AT24C01A/02SC/04SC/08SC/16SC provide 1024/2048/4096/8192/16384 bits of serial, electrica
lly-erasable, and programmable read-only memory (EEPROM) orga-nized as 128/256/512/1024/2048 words of 8 bits each. The devices are optimized for use in smart card applications where low-power and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information, pages 12–13). All devices are functionally equivalent to Atmel serial EEPROM products offered in standard IC packages (PDIP , SOIC, TSSOP ,MAP), with the exception of the slave address and write protect functions, which are not required for smart card applications.Figure 1. Card Module Contact巴菲特:从100元到160亿
2
AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04
Figure 2. Block Diagram
功率模块Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.
Memory Organization
AT24C01ASC, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing.
AT24C02SC, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing.
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
aurita
3
AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04
AT24C04SC, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.
AT24C08SC, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address random word addressing.
AT24C16SC, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address random word addressing.
Pin Capacitance
DC Characteristics
AC CC 2.V IL min and V IH max are reference only and are not tested.
AC Characteristics
Table 2. Pin Capacitance (1)
Applicable over recommended operating range from T = 25°C, f = 1.0 MHz, V = +2.7V
Table 3. DC Characteristics (1)
(1)
4
AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04交流网
A CC (unless otherwise noted)2.This parameter is characterized and is not 100% tested.
Device Operation
CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL-low time periods (see Figure 3 on page 5). Data changes during SCL-high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 4 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. Each word requires the receiver to acknowledge that it has received a valid command or data byte. During the transmission of commands from the host to the EEPROM, the EEPROM will send a zero to the host to acknowledge that it has received a valid command byte. This occurs on the ninth clock cycle of the com-mand byte. During read operations, the host will send a zero to the EEPROM to acknowledge that it has received a valid data byte and that it requests the next sequen-tial data byte to be transmitted during the subsequent eight clock cycles. This occurs on the ninth clock cycle of the data byte. If the host does not transmit this acknowledge bit,the EEPROM will disable the read operation and return to standby mode.
STANDBY MODE: The AT24C01ASC/02SC/04SC/08SC/16SC feature a low-power standby mode that is enabled upon power-up and after the receipt of the stop bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss, or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.
2.Look for SDA high in each cycle while SCL is high.
3.Create a start condition as SDA is high.
Table 4. AC Characteristics (1) (Continued)
5
AT24C01ASC/02SC/04SC/08SC/16SC
1610B –SEEPR –04/04
Timing Diagrams
Bus Timing
Figure 1. Bus Timing
Note:SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 2. Write Cycle Timing
Notes:
1.The write cycle time t WR is the time from a valid stop condition of a write sequence to
the end of the internal clear/write cycle.2.SCL: Serial Clock, SDA: Serial Data I/O
Data Validity
Figure 3.
Data Validity
6
5羟甲基糠醛AT24C01ASC/02SC/04SC/08SC/16SC
Start and Stop Definition
Figure 4. Start and Stop Definition
Output Acknowledge
Figure 5.
Output Acknowledge
豫公网安备41160202000603
站长QQ:729038198
关于我们
投诉建议