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1996 Microchip Technology Inc.DS11183D-page 1

24C01A/02A/04A

FEATURES

•Low power CMOS technology •Hardware write protect

•Two wire serial interface bus, I 2 C ™ compatible • 5.0V only operation

•Self-timed write cycle (including auto-erase)•Page-write buffer

•1ms write cycle time for single byte

•1,000,000 Erase/Write cycles guaranteed •Data retention >200 years •8-pin DIP/SOIC packages

•

amazing things

Available for extended temperature ranges DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a signif-icant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block.The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus.

This device offers fast (1ms) byte write and extended (-40 ° C to 125 ° C) temperature operation. It is recommended that all other applications use Microchip’s 24LCXXB.

-Commercial (C):0˚C to +70˚C -Industrial (I):-40˚C to +85˚C -Automotive (E):-40˚C to +125˚C

24C01A

24C02A 24C04A Organization 128 x 8258 x 8 2 x 256 x 8Write Protect None 080-0FF 100-1FF Page Write Buffer

2 Bytes

8 Bytes

PACKAGE TYPES

BLOCK DIAGRAM

NC SS CC A0A1NC A2NC

V 1234567

141312NC SCL SDA NC

1110WP V NC * “TEST” pin in 24C01A

24C01A 24C02A 24C04A

A0A1A2V SS

1234

8765

V CC WP*SCL SDA

A0A1A2V SS

1234

8765

V CC WP*SCL SDA

DIP

8-lead

SOIC

14-lead SOIC

Vcc Vss

SDA

SCL

Data Buffer (FIFO)Data Reg.

Vpp

R/W Amp

Memory Array

A d d r e s s P o i

n t

e r

A0 to A7Increment

Slave Addr.

Control Logic

A0A1A2WP

1K/2K/4K 5.0V I 2 C ™

Serial EEPROMs

I 2 C is a trademark of Philips Corporation.

国际化学年This document was created with FrameMaker 404

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24C01A/02A/04A

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

V CC ...................................................................................7.0V All inputs and V SS ...............-0.6V to V CC +1.0V .-65˚C to +150˚C Ambient temp. with .-65˚C to +125˚C Soldering temperature of leads (10 seconds).............+300˚C ESD protection on 4 kV

*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the

device. This is a stress rat-ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name Function

A0No Function for 24C04A only, Must be connected to V CC or V SS A0, A1, A2Chip Address Inputs V SS Ground

SDA Serial Address/Data I/O SCL Serial Clock

TEST (24C01A only) V CC or V SS WP Write Protect Input V

+5V Power Supply

TABLE 1-2:DC CHARACTERISTICS

FIGURE 1-1:BUS TIMING START/STOP

CC = +5V ( ± 10%)

Commercial (C):Tamb =0 ° C to +70 ° C Industrial (I):Tamb =-40 ° C to +85 ° C Automotive (E):Tamb =-40 ° C to +125 ° C

Parameter

Symbol

Min.

Max.

Units Conditions

V CC detector threshold V TH 2.8 4.5V SCL and SDA pins:

High level input voltage Low level input voltage Low level output voltage V IH V IL V OL V CC x 0.7-0.3V CC + 1V CC x 0.30.4V V V I OL = 3.2 mA (SDA only)

A1 & A2 pins:

High level input voltage Low level input voltage V IH V IL V CC - 0.5-0.3V CC + 0.50.5

V V Input leakage current I

—10 µ A V IN = 0V to V CC Output leakage current I

LO —10 µ A V OUT = 0V to V CC

Pin capacitance (all inputs/outputs)C IN , C OUT —7.0pF V IN /V OUT = 0V (Note) Tamb = +25˚C, f = 1 MHz

Operating current I CC Write — 3.5

mA F CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = 0˚C to +70˚C

I CC Write

—

4.25

F CLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = (I) and (E)I

CC Read

—750 µ A

V CC = 5V, Tamb= (C), (I) and (E)

Standby current I

CCS

—100 µ A SDA=SCL=V

=5V (no PROGRAM active)

Note:This parameter is periodically sampled and not 100% tested

T SU :STA

T HD :STA

日本雅乐

V HYS

T SU :STO

START STOP

SCL

SDA

元器件交易网b2b

1996 Microchip Technology Inc.DS11183D-page 3

24C01A/02A/04A

TABLE 1-3:AC CHARACTERISTICS

FIGURE 1-2:BUS TIMING DATA

Parameter

Symbol Min.Typ Max.Units Remarks

Clock frequency F CLK ——100kHz Clock high time T HIGH 4000——ns Clock low time

T LOW 4700——ns SDA and SCL rise time T R ——1000ns SDA and SCL fall time T F ——300ns START condition hold time T HD :S TA 4000——ns After this period the ﬁrst clock pulse is generated START condition setup time T SU :S TA 4700——ns Only relevant for repeated START condition

粘滞阻尼系数

Data input hold time T HD :D AT 0——ns Data input setup time T SU :D AT 250——ns

Data output delay time T AA 300—3500(Note 1)

STOP condition setup time T SU :S TO 4700——ns Bus free time四甲基胍

T BUF

4700

—

Time the bus must be free before a new transmission can start

Input ﬁlter time constant (SDA and SCL pins)T I ——100ns Program cycle time

—

.41ms Byte mode

.4N N ms Page mode, N=# of bytes

Endurance —1M —

—

cycles

25 °

C, Vcc = 5.0V, Block

Mode (Note 2)

Note 1:As transmitter the device must provide this internal minimum delay time to bridge the undeﬁn

ed region (min-imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2:This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

T SU :STA

T F

T LOW

T HIGH

T R

T HD :DAT

T SU :DAT T SU :STO

T HD :STA

T BUF

T AA

T SP

T HD :STA

SCL

SDA IN

SDA OUT

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24C01A/02A/04A

2.0

FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions, while the 24C01A/02A/04A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.

Up to eight 24C01/24c02s can be connected to the bus,selected by the A0, A1 and A2 chip address inputs. Up to four 24C04As can be connected to the bus, selected by A1 and A2 chip address inputs. A0 must be tied to V CC or V SS for the 24C04A. Other devices can be con-nected to the bus but require different device codes than the 24C01A/02A/04A (refer to section Slave Address).

心理月刊杂志3.0BUS CHARACTERISTICS

The following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.

•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have been deﬁned (Figure 3-1).

3.1Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

3.4Data Valid (D)

The state of the data line represents valid data when,after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.

3.5Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of th

e acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

Note:

The 24C01A/02A/04A does not generate any acknowledge bits if an internal pro-gramming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(A)

(C)

START CONDITION

ADDRESS OR ACKNOWLEDGE

VALID DATA ALLOWED TO CHANGE

STOP CONDITION

SCL

SDA

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24C01A/02A/04A

4.0SLAVE ADDRESS

The chip address inputs A0, A1 and A2 of each 24C01A/02A/04A must be externally connected to either V CC or ground (V SS ), assigning to each 24C01A/02A/04A a unique address. A0 is not used on the 24C04A and must be connected to either V CC or V SS . Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the bus. Chip selection is then accomplished through software by setting the bits A0, A1 and A2 of the slave address to the corresponding hard-wired logic levels of the selected 24C01A/02A/04A.After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24C01A/02A/04A, followed by the chip address bits A0, A1 and A2. In the 24C04A, the seventh bit of that byte (A0) is used to select the upper block (addresses 100—1FF) or the lower block (addresses 000—0FF) of the array.

The eighth bit of slave address determines if the master device wants to read or write to the 24C01A/02A/04A (Figure 4-1).

The 24C01A/02A/04A monitors the bus for its corre-sponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.

FIGURE 4-1:

SLAVE ADDRESS ALLOCATION

5.0BYTE PROGRAM MODE

In this mode, the master sends addresses and one data byte to the 24C01A/02A/04A.

Following the START signal from the master, the device code (4-bits), the slave address (3-bits), and the R/W bit, which is logic LOW, are placed onto the bus by the master. This indicates to the addressed 24C01A/02A/04A that a byte with a word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01A/02A/04A. After receiving the acknowledge of the 24C01A/02A/04A, the master device transmits the data word to be written into the addressed memory location.The 24C01A/02A/04A acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle of the 24C01A/02A/04A (Figure 6-1).

SLAVE ADDRESS

1010A2A1A0

R/W A

START

READ/WRITE

6.0

PAGE PROGRAM MODE

To program the 24C01A/02A/04A, the master sends addresses and data to the 24C01A/02A/04A which is the slave (Figure 6-1 and Figure 6-2). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address, and the R/W bit which is deﬁned as a logic LOW for a write. This indi-cates to the addressed slave that a word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock pulse. When the word address is received by the 24C01A/02A/04A, it places it in the lower 8 bits of the address pointer deﬁning which memory location is to be written. (The A0 bit transmitted with the slave address is the ninth bit of the address pointer for the 24C04A). The 24C01A/02A/04A will generate an acknowledge after every 8-bits received and store them consecutively in a RAM buffer until a STOP condition is detecte

d. This STOP condi-tion initiates the internal programming cycle. The RAM buffer is 2 bytes for the 24C01A/02A and 8 bytes for the 24C04A. If more than 2 bytes are transmitted by the master to the 24C01A/02A, the device will not acknowl-edge the data transfer and the sequence will be aborted. If more than 8 bytes are transmitted by the master to the 24C04A, it will roll over and overwrite the data beginning with the ﬁrst received byte. This does not affect erase/write cycles of the EEPROM array and is accomplished as a result of only allowing the address registers bottom 3 bits to increment while the upper 5bits remain unchanged.

If the master generates a STOP condition after trans-mitting the ﬁrst data word (Point ‘P’ on Figure 6-1), byte programming mode is entered.

The internal, completely self-timed PROGRAM cycle starts after the STOP condition has been generated by the master and all received data bytes in the page buffer will be written in a serial manner.

The PROGRAM cycle takes N milliseconds, whereby N is the number of received data bytes (N max = 8 for 24C04A, 2 for 24C01A/02A).

元器件交易网b2b

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