EDA基础总结
综述部分
1.EDA的中文全称为电子设计自动化,英文全名为Electronic Design Automation;
2.EDA平台常用的两种输入电路的方法是：电路原理图输入法、HDL输入法; 3.EDA平台工作流程：电路输入、综合优化、功能仿真、布局布线、门级仿真; 数字电路部分
1.EDA中常用的仿真语言为Verilog和VHDL;
2.VHDL其英文全名为VHSIC Hardware Description Language,而VHSIC则是Very High Speed Intergeraterd Circuit的缩写词,意为甚高速集成电路,故VHDL其准确的中文译名为甚高速集成电路的硬件描述语言; 3.Verilog HDL其英文全名为Verilog Hardware Decription Language,HDL中文译名为硬件描述语言;
4.Verilog和VHDL的比较
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共同点：能形式化地抽象表示电路的行为和结构；支持逻辑设计中层次与范围的描述；可借用高级语言的精巧结构来简化电路行为的描述；具有电路仿真与验证机制以保证设计的正确性；支持电路描述由高层到低层的综合转换；硬件描述与实现工艺无关；便于文档管理；易于理解和设计重用;不同点：Verilog在系统级抽象方面略差,VHDL在门级开关电路方面略差;
5.软核、固核和硬核
软核：功能经过验证的、可综合的、实现后电路结构总门数在5000门以上的Verilog模型;
固核：在某一种现场可编程门列器件上实现的经验证是正确的,且总门数在5000门以上的电路结构编码文件;
硬核：在某一种专用集成电路工艺的器件上实现的,经验证是正确的,且总门数在5000门以上的电路结构版图掩膜;
6.自顶向下Top Down设计
7.自底向上Down Top设计
8.名词解释：
ASIC：Application Specific Integrated Circuit,专用集成电路;
FPGA：Field Programmable Gate Array,现场可编程门阵列;
PLD：Programmable Logic Device,可编程逻辑器件;
Verilog编程题：
数据比较器2位
//数据比较器
module compare equal, a, b;
input a,b;
output equal;
reg equal;
always a or b
if a == b
equal = 1;
else
equal = 0;
endmodule
//数据比较器测试代码
刚度系数
`timescale 1ns/1ns
`include "./1-1.v"
module t;
reg a,b;
wire equal;
initial
begin
a=0;
b=0;
100 a=0; b=1;
100 a=1; b=1;
100 a=1; b=0;
100 a=0; b=0;
100 $stop;
end
compare m.equalequal, .aa, .bb;
endmodule
数据比较器8位
module compare8equal, a, b;
input 7:0a, b;
output equal;
reg equal;
always a or b
if a > b
begin
equal = 1;
end
else
begin
equal = 0;
end
endmodule
分频器
module half_clkreset, clk_in, clk_out;
input clk_in, reset;
output clk_out;
reg clk_out;
always posedge clk_in
begin
ifreset clk_out = 0;
else clk_out = ~clk_out;
end
endmodule
10M时钟分频为500K
module fdivision RESET, MB, KB;
input MB, RESET;
output KB;
reg KB;
reg 7:0 j;
always posedge MB
if RESET
begin
KB <= 0;
j <= 0;
end
else
begin
if j == 19
begin j <= 0;
KB <= ~KB;
end
else
j <= j+1;
end
endmodule
译码电路
`define plus 3'd0
`define minus 3'd1
万方数据资源`define band 3'd2
`define bor 3'd3
`define unegate 3'd4
module aluout, opcode, a, b;
output7:0 out;
reg7:0 out;
input2:0 opcode;
input7:0 a,b;
always opcode or a or b
begin
caseopcode
`plus: out = a + b;
`minus: out = a - b;
`band: out = a & b;
`bor: out = a | b;
`unegate: out = ~a;
default: out = 8'hx;迷惘的一代
endcase
end
endmodule
八路数据选择器
module selecting8addr, in1, in2, in3, in4, in5, in6, in7, in8, dataout, reset;
input 2:0 addr;
input 3:0 in1,in2,in3,in4,in5,in6,in7,in8;
input reset;
output 3:0 dataout;
reg 3:0 dataout;
always addr or in1 or in2 or in3 or in4 or in5 or in6 or in7 or in8 or reset
begin
lte-a ifreset
caseaddr
3'b000: dataout = in1;
3'b001: dataout = in2;
3'b010: dataout = in3;
3'b011: dataout = in4;
3'b100: dataout = in5;
3'b101: dataout = in6;
3'b110: dataout = in7;
3'b111: dataout = in8;
endcase
else
dataout = 0;
end
endmodule
逻辑运算电路
module tryfunctclk, n, result, reset;
output31:0 result;
input3:0 n;
input reset, clk;
reg31:0 result;
中小企业erp always posedge clk
begin
if reset
result <=0;
else
begin
result <= nfactorialn/n2+1;
end
end
function 31:0 factorial;
input 3:0 operand;
reg 3:0 index;
begin
factorial = operand 1:0;
for index = 2; index <= operand; index = index + 1
factorial = index factorial;
end
endfunction
endmodule
module tryfunctclk, n, result, reset;
output31:0 result;
input3:0 n;
input reset, clk;
reg31:0 result;
always posedge clk
begin
if reset
result <=0;
else
begin
result <= nfactorialn/n2+1;
end
end
function 31:0 factorial;
input 3:0 operand;
reg 3:0 index;
begin
factorial = operand 1:0;
for index = 2; index <= operand; index = index + 1
factorial = index factorial;
end
endfunction
endmodule
高速排序组合逻辑
module sort4ra, rb, rc, rd, a, b, c, d;
output3:0 ra, rb, rc, rd;
input3:0 a, b, c, d;
reg3:0 ra, rb, rc, rd;
reg3:0 va, vb, vc, vd;
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