KAD2708C
300 Unicorn Park Dr., Woburn, MA 01801 Sales: 1-781-497-0060 Sales@kenetinc
Description
The Kenet KAD2708C is the industry’s lowest power, 8-bit, high performance Analog-to-Digital conv
erter. The converter runs at sampling rates up to 275MSPS, and is fabricated with Kenet’s proprietary FemtoCharge® CMOS technology. Users can now obtain industry-leading SNR and SFDR specifications while nearly halving power consumption. Sampling rates of 210, 170 and 105MSPS are also available in the same pin-compatible package and in versions with 10-bit resolution. Kenet’s KAD2708L offers this performance with LVDS outputs. All are available in 68-pin RoHS-compliant QFN packages with exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85°C).
Key Specifications
• SNR of 48.8dB at Nyquist • SFDR of 68dBc at Nyquist
• Power consumption ≤ 265mW at f S = 275MSPS
Features
• On-chip reference
• Internal track and hold
• 1.5V PP differential input voltage • 600MHz analog input bandwidth • Two’s complement or binary output • Over-range indicator
• Selectable ÷2 Clock Input • LVCMOS compatible outputs
Applications
• High-Performance Data Acquisition • Portable Oscilloscope • Medical Imaging • Cable Head Ends
• Power-Amplifier Linearization
• Radar and Satellite Antenna Array Processing • Broadband Communications
• Local Multipoint Distribution System (LMDS) •
Communications Test Equipment
8-Bit, 275MSPS Analog-to-Digital Converter
Resolution, Speed LVDS Outputs LVCMOS Outputs
10 Bits 275MSPS KAD2710L-27 KAD2710C-27 8 Bits 275MSPS KAD2708L-27 KAD2708C-27 10 Bits 210MSPS KAD2710L-21 KAD2710C-21 8 Bits 210MSPS KAD2708L-21 KAD2708C-21 10 Bits 170MSPS KAD2710L-17 KAD2710C-17 8 Bits 170MSPS KAD2708L-17 KAD2708C-17 10 Bits 105MSPS KAD2710L-10 KAD2710C-10 8 Bits 105MSPS
KAD2708L-10
KAD2708C-10
8 Bits 350MSPS KAD2708L-35
Table 1. Pin-Compatible Products
Absolute Maximum Ratings1
1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure
to maximum conditions for extended periods may affect device reliability.
Thermal Impedance
2. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and equipment, and may discharge
through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been utilized in the design of this prod-
uct. However, reasonable care must be taken in the storage and handling of ESD sensitive
products. Contact Kenet for the specific ESD sensitivity rating of this product.
现代科技成就Parameter Min
Max
Unit AVDD2 to AVSS -0.4 2.1 V
OVDD2 to OVSS -0.4 2.1 V
Analog Inputs to AVSS -0.4 AVDD3 + 0.3 V
Clock Inputs to AVSS -0.4 AVDD2 + 0.3 V
Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4 AVDD3 + 0.3 V
Logic Inputs to OVSS (RST, 2SC) -0.4 OVDD2 + 0.3 V
Operating Temperature -40 85 °C
Storage Temperature -65 150 °C
Junction Temperature 150 °C
AVDD3 to AVSS -0.4 3.7 V
Logic Output Currents 10 mA
CMOS Output Currents 20 mA
VREF TO AVSS -0.4 AVDD3 + 0.3 V
Analog Output Currents 10 mA
Parameter Symbol
Unit
Junction to Paddle2ΦJP 30 °C/W
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V. T A = -40°C to +85°C, Typ values at 25°C. f SAMPLE = 275MSPS f IN = Nyquist.
DC Specifications
Max
Typ
Units
Min
Parameter Symbol
Conditions
Power Requirements
1.8V Analog Supply Voltage AVDD2 1.7 1.8 1.9 V
黑箱法
3.3V Analog Supply Voltage AVDD3 3.15 3.3 3.45 V
1.8V Output Supply Voltage OVDD 1.7 1.8 1.9 V
1.8V Analog Supply Current I AVDD244 mA
3.3V Analog Supply Current I AVDD341 mA
1.8V Output Supply Current I OVDD 26 mA
mW
Power Dissipation P D261
Analog Specifications
异丙酚AC Specifications
Parameter Symbol Conditions Min Typ Max Units
Analog Input
Full-Scale Differential Analog Input Voltage V IN 1.4 1.5 1.6 V PP Gain Temperature Coefficient A VTC Full Temp 90 ppm/ºC Full Power Bandwidth FPBW
600
MHz
Clock Input
Sampling Clock Frequency Range f SAMPLE 50 275 MHz CLKP, CLKN P-P Differential Input Voltage V CDI 0.5 1.8 V PP CLKP, CLKN Differential Input Resistance R CDI 10 M Ω CLKP, CLKN Common-Mode Input Voltage V CCI
0.9
V
Reference
Internal Reference Voltage
沉思者
V REF 1.18 1.21 1.24 V Reference Voltage Temperature Coefficient V RTC Full Temp 38 ppm/°C
Common-Mode Output Voltage V CM
0.86
V
Parameter Symbol Conditions Min Typ Max Units
Signal to Noise Ratio SNR Full Temp 45.8 48.8 dB Signal to Noise and Distortion SINAD
Full Temp
45.7 48.7 dB Effective Number of Bits
ENOB Full Temp
7.3 7.8 Bits Spurious Free Dynamic Range SFDR Full Temp 63 68 dBc Two-Tone SFDR 2TSFDR f 1=133MHz, f 2=135MHz 67 dBc Differential Nonlinearity DNL -0.3 ±0.2 0.4 LSB Power
Supply Rejection Ratio PSRR 42 66 dB Word Error Rate
WER
1x10-12
Integral Nonlinearity INL -0.8 ±0.2 0.8 LSB
Digital Specifications
cnki
Max
Units
Typ
Min
Parameter Symbol
Conditions
Inputs
High Input Voltage (VREFSEL) VREFSEL V IH 0.8*AVDD3 V
V Low Input Voltage (VREFSEL) VREFSEL V IL0.2*AVDD3
Input Current High (VREFSEL) VREFSEL I IH VIN = AVDD3 0 1 10 µA
Input Current Low (VREFSEL) VREFSEL I IL VIN = AVSS 25 65 75 µA
High Input Voltage (CLKDIV) CLKDIV V IH 0.8*AVDD3 V
V Low Input Voltage (CLKDIV) CLKDIV V IL0.2*AVDD3
Input Current High (CLKDIV) CLKDIV I IH VIN = AVDD3 25 65 75 µA
Input Current Low (CLKDIV) CLKDIV I IL VIN = AVSS 0 1 10 µA
High Input Voltage (RST,2SC) RST,2SC V IH 0.8*OVDD2 V
V Low Input Voltage (RST,2SC) RST,2SC V IL0.2*OVDD2
Input Current High (RST,2SC) RST,2SC I IH VIN = OVDD 0 1 10 µA
Input Current Low (RST,2SC) RST,2SC I IL VIN = OVSS 25 50 75 µA
Input Capacitance C DI 3 pF
CMOS Outputs
Voltage Output High V OH 1.8 V
Voltage Output Low V OL0 V
Output Rise Time t R 1.8 ns
Output Fall Time t F 1.4 ns
Timing Diagram
Figure 1. LVCMOS Timing Diagram
Timing Specifications
Parameter Symbol Min Typ Max Units
Aperture Delay t A 1.7 ns
RMS Aperture Jitter
j
A
200
fs
Input Clock to Data Propagation Delay
t
PD
1.8 ns Input Clock to Output Clock Propagation Delay t CPD 1.3 ns Output Clock to Data Propagation Delay t
DC
470
ps
Output Data to Output Clock Setup Time t SU 3 ns Output Clock to Output Data Hold Time t H
75 ps Latency (Pipeline Delay) L
28
cycles
Over Voltage Recovery
t OVR 1
cycle
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