浙江大学20 14–20 15学年秋冬学期
《数字系统设计II》课程期末考试试卷课程号：111C0130，开课学院：_信息与电子工程学系_ 考试形式：√闭、开卷（请在选定项上打√）
允许带1张A4 大小的手写资料和计算器入场
考试日期：2015 年1月24 日，考试时间：120 分钟
考生姓名：学号：所属院系（专业）：_
光谱学与光谱分析
This question considers the basic MIPS 5-stage pipeline (IF, ID, EX, MEM, WB). 1)Assume that each of the above steps takes the amount of time specified in the
Given the times for the datapath stages listed above, what would the clock period be for the entire datapath? In a pipelined datapath, assuming no hazards or stalls, how many seconds will it take to execute an instruction?
2)Assume that you have the following sequence of pipelined instructions:
lw $6, 0($7)
add $8, $9, $10
sub $11, $6, $8
Where will the data operands that are processed during the EX stage of the subtract (sub) instruction come from? (Consider two situations: (1) there is no forwarding, and (2) there is full forwarding.)
2. PIPELINE (13 points):
Use the following MIPS code fragment:
I1: ADDI $3, $0, 100 # $3 = 100
I2: ADD $4, $0, $0 # $4 = 0
Loop:
I3: LW $5, 0($1) # $5 = MEM[$1]
I4: ADD $4, $4, $5 # $4 = $4 + $5
I5: LW $6, 0($2) # $6 = MEM[$2]
I6: SUB $4, $4, $6 # $4 = $4 – $6
I7: ADDI $1, $1, 4 # $1 = $1 + 4
I8: ADDI $2, $2, 4 # $2 = $2 + 4
I9: ADDI $3, $3, -1 # $3 = $3 – 1
I10: BNE $3, $0, Loop #if ($3 != 0) goto Loop
1) Show the timing of one loop iteration on the 5-stage MIPS pipeline without
forwarding hardware. Complete the timing table, shown as Table Q2.1in the next page, showing all the stall cycles. Assume that the branch will stall the pipeline for 1 clock cycle only.
2) According to the timing diagram of Table Q2.1, compute the number of clock
cycles and the average CPI to execute ALL the iterations of the above loop.
Table Q2.1 Timing of one loop iteration on the 5-stage MIPS pipeline without forwarding hardware. (F: instruction fetch, D: instruction decode, X: execute, M: memory access, W: write back.) We assume that the register write is done in the first half of the clock cycle and that register reads are done in the second half of the cycle.
3 / 10
3. CACHE (10 points):
A 16-byte cache has 8-byte blocks, has 2 sets, and is 2-way set-associative. The cache initially is empty (all valid bits are off: indicated by a blank box in the table below). The cache receives requests in the sequence listed in Table Q3.1. For each address in the sequence (a) split it into the tag, index, and offset; (b) categorize the access as a hit, a compulsory miss, a confict miss, or a capacity miss (You can abbreviate hit=H, Compulsory=O, Confict=F, Capacity=P); (c) show the new contents of the cache after the access----write the tags for each way, and note which way is LRU.
The first one is done for you.
Table Q3.1
4. VIRTUAL MEMORY (9 points):
豪杰超级解霸2000Describe the number of bits required in each entry of a TLB that has the following characteristics:
周芷若的乳头
· Virtual addresses are 32 bits wide
· Physical addresses are 31 bits wide
· The page size is 2K bytes
· The TLB contains 16 entries of the page table
· The TLB is direct-mapped
Note:
Each entry of the TLB contains the following items:
- a valid bit
- the physical page number of the desired virtual page
- a tag used to see if the desired entry of the page table is stored in the TLB
- ignore the “dirty” bit
1)Physical page number：
2)Tag:
3)The number of bits required in each entry of a TLB:
5. CHOICE (60 points) (note: only one is correct):
(1)Which of the following descriptions is the reason why binary expression is still used in
computer technique. ( )
A: It saves components.
B: It has fast computing ability.
C: It is decided by the physical property of components.
抚顺育才中学D: It has nice convenience in coping with information.
(2)Which one is not one of the five classic components of a computer? ( )
A: Input
B: Bus
C: Memory
D: Output
(3)What is the range of exponent of IEEE 745 single precision? ( )
A: 1~254
B: -128~126
C: -126 ~127
D:-127~128
(4)Assume a test program A is running on computer A. It consumes 100 seconds totally, 90
for CPU and 10 for I/O. Now, the CPU speed improved by 50% and I/O spee d hasn‟t changed. How much time it takes to run program A now? ( )
A: 55 sec
B: 60 sec
C: 65 sec
D: 70 sec
(5)A simple program is running on a 32-bit computer. x(int), y(short), z are variables in this
program. If x = 127 and y = -9, what are the contents in computer memory after executing the assigning statement z = x + y? ( )
A: x = 0000007FH, y = FFF9H, z = 0076H
B: x = 0000007FH, y = FFF9H, z = 00000076H
C: x = 0000007FH, y = FFF7H, z = 0076H
D: x = 0000007FH, y = FFF7H, z = 00000076H
(6)Which of the following instructions could this single-cycle datapath description be
referring to? ( )
Description :Two source registers (ReadReg) and one destination register (WriteReg) are selected, and the values are read from the source registers and sent as input to the ALU.
The ALU operation is performed, the result is written to the destination register, and the PC is updated.
A: add B: ori C: li D: sll
(7)The following commands were used to store the contents of registers $s0 and $s1 onto the
stack:
addi $sp, $sp, -8
sw $s0, 0($sp)
bppv
sw $s1, 4($sp)
# insert various unrelated instructions here
Assuming that neither the stack pointer nor the stack has been changed during the "various unrelate
d instructions" part, which of the following would allow you to recover the contents of $s0 and $s1 while returning $sp to its original (pre-decremented) value? ( )
A: addi $sp, $sp, 8; lw $s0, 4($sp); lw $s1, 0($sp)
B: addi $sp, $sp, 8; lw $s0, 0($sp); lw $s1, 4($sp)
C: lw $s0, 4($sp); lw $s1, 0($sp); addi $sp, $sp, 8
D: lw $s0, 0($sp); lw $s1, 4($sp); addi $sp, $sp, 8
(8)How the cache conflict misses will be affected by the following modifications? ( )
Assume the baseline cache is set associative.
(a). Double the associativity while keep the capacity and line size constant
(b). Double the number of sets while keep the capacity and line size constant
A: Decrease; Increase
B: Increase; Decrease
C: Increase; Increase
D: Decrease; Decrease
(9)Which of the following statements about multiplication and division is incorrect? ( ) A: Integer multiplications takes an input two 32-bit values and returns a 64-bit value
B: The result of a multiplication is stored in a read-only (for the programmer at least) "product" register
C: The product of two numbers is accesssed using two separate instructions - mfhi to get bits 0-31 (the rightmost bits), and mflo to get bits 32-63
D: The div command stores the quotient and the remainder in the product register, and the two can be accessed using mfhi and mflo
(10)Which of the following is generally true about a design with two levels of caches? ( ) A: First-level caches are more concerned about hit time, and second-level caches are more concerned about miss rate.
B: First-level caches are more concerned about miss rate, and second-level caches are more concerned about hit time.
C: Second-level caches often use lower associativity than first-level caches given the focus of reducing miss rates.
医疗供应链金融D: Second-level caches are as fast as first-level caches.
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