The L TC ®2209 is a 160Msps 16-bit A/D converter designed
for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.The L TC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±5LSB INL, ±1LSB DNL (no missing codes).
The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V .
The ENC + and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al-lows high performance at full speed with a wide range of clock duty cycles.
n
Telecommunications n Receivers
n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
n
Sample Rate: 160Msps n 77.3dBFS Noise Floor n 100dB SFDR
n SFDR >84dB at 250MHz (1.5V P-P Input Range)n PGA Front End (2.25V P-P or 1.5V P-P Input Range)n 700MHz Full Power Bandwidth S/H n Optional Internal Dither
n Optional Data Output Randomizer n LVDS or CMOS Outputs n Single 3.3V Supply
n Power Dissipation: 1.45W n Clock Duty Cycle Stabilizer n Pin-Compatible Family:
130Msps: L TC2208 (16-Bit), L TC2208-14 (14-Bit) 105Msps: L TC2217 (16-Bit)n 64-Pin (9mm × 9mm) QFN Package
64k Point FFT , f IN = 15.1MHz,
–1dBFS, PGA = 0
FEATURES
APPLICATIONS
DESCRIPTION
T YPICAL APPLICATION L , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TA01
ADC CONTROL INPUTS
FREQUENCY (MHz)
0A M P L I T U D E (d B F S )
–100–30–20–10020
40502209 TA01b
–120–60–80–110–40–50–130
–70–901030706080
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION
TEMPERATURE RANGE L TC2209CUP#PBF L TC2209CUP#TRPBF L TC2209UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2209IUP#PBF L TC2209IUP#TRPBF L TC2209UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION
TEMPERATURE RANGE L TC2209CUP L TC2209CUP#TR L TC2209UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2209IUP
L TC2209IUP#TR
L TC2209UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container .For more information on lead free part marking, go to: www.linear /leadfree/ For more information on tape and reel specifi cations, go to: www.linear /tapeandreel/
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
OV DD = V DD (Notes 1 and 2)
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)
Supply Voltage (V DD ) ...................................–0.3V to 4V Digital Output Ground Voltage (OGND) ........–0.3V to 1V Analog Input Voltage (Note 3) ......–0.3V to (V DD + 0.3V)Digital Input Voltage .....................–0.3V to (V DD + 0.3V)Digital Output Voltage ................–0.3V to (OV DD + 0.3V)Power Dissipation .............................................2500mW Operating Temperature Range
L TC2209C ................................................0°C to 70°C –40°C to 85°C Storage Temperature Range ...................–65°C to 150°C Digital Output Supply Voltage (OV DD ) ..........–0.3V to 4V
ORDER INFORMATION
CONVERTER CHARACTERISTICS
PARAMETER CONDITIONS
MIN
TYP MAX UNITS Integral Linearity Error Differential Analog Input (Note 5) T A = 25°C ±1.5±5LSB Integral Linearity Error Differential Analog Input (Note 5)l ±1.5±5.5LSB Differential Linearity Error Differential Analog Input l ±0.3±1LSB Offset Error (Note 6)
l
±2 ±10mV Offset Drift ±10μV/°C Gain Error External Reference l
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通知±0.2 ±2
%FS
Full-Scale Drift Internal Reference
External Reference ±30±15ppm/°C ppm/°C T ransition Noise
External Reference
3
LSB RMS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at T A = 25°C. A IN = –1dBFS. (Note 4)
ANALOG INPUT
DYNAMIC ACCURACY SYMBOL PARAMETER
CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN + – A IN –) 3.135V ≤ V DD ≤ 3.465V 1.5 or 2.25V P-P V IN, CM Analog Input Common Mode Differential Input (Note 7)l 1 1.25
1.5V I IN Analog Input Leakage Current 0V ≤ A IN +, A IN – ≤ V DD l –11μA I SENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ V DD
l
–3
3
μA I MODE MODE Pin Pull-Down Current to GND 10μA I LVDS LVDS Pin Pull-Down Current to GND 10μA
C IN Analog Input Capacitance Sample Mode ENC + < ENC –Hold Mode ENC + > ENC –
6.6
1.8 pF
pF
t AP Sample-and-Hold
Aperture Delay Time 1.0ns t JITTER Sample-and-Hold
Acquisition Delay Time Jitter 70fs RMS
CMRR Analog Input
Common Mode Rejection Ratio 1V < (A IN + = A IN –) <1.5V 80dB BW-3dB
Full Power Bandwidth
R S < 25Ω
700
MHz
SYMBOL PARAMETER CONDITIONS
MIN TYP MAX UNITS SNR
Signal-to-Noise Ratio
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77.175
dBFS dBFS 30MHz Input (2.25V Range, PGA = 0) T A = 25°C 30MHz Input (2.25V Range, PGA = 0)30MHz Input (1.5V Range, PGA = 1)
l 7675.6
7776.874.9dBFS dBFS dBFS 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1)
76.974.7
dBFS dBFS 140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) T A = 25°C 140MHz Input (1.5V Range, PGA = 1)l
73.472.9
76.674.473.9dBFS dBFS dBFS 250MHz Input (2.25V Range, PGA = 0)250MHz Input (1.5V Range, PGA =1 )
7573.5dBFS dBFS SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)
100100
dBc dBc 30MHz Input (2.25V Range, PGA = 0) T A = 25°C 30MHz Input (2.25V Range, PGA = 0) 30MHz Input (1.5V Range, PGA = 1)l
8685
9594100dBc dBc dBc 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1)
8888dBc dBc 140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) T A = 25°C 140MHz Input (1.5V Range, PGA = 1)l
8482
848888dBc dBc dBc 250MHz Input (2.25V Range, PGA = 0)250MHz Input (1.5V Range, PGA = 1)
7584
dBc dBc
玺印
The
l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. A IN = –1dBFS unless otherwise noted. (Note 4)
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SFDR Spurious Free
Dynamic Range
4th Harmonic or Higher 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
100
100
dBc
dBc 30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l88100
100
dBc
dBc 70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
100
100
dBc
dBc 140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)l87
95
95
dBc
dBc 250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
90
90
dBc
dBc
S/(N+D)Signal-to-Noise Plus Distortion
Ratio 5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
77.1
75
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dBFS 30MHz Input (2.25V Range, PGA = 0) T A = 25°C
30MHz Input (2.25V Range, PGA = 0)
胆汁质30MHz Input (1.5V Range, PGA = 1)
l
75.9
75.5
77
76.7
74.9
dBFS
dBFS
dBFS 70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
76.8
74.7
dBFS
dBFS 140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) T A = 25°C
140MHz Input (1.5V Range, PGA = 1)l
73
72.7
75.7
74.2
74.2
dBFS
dBFS
dBFS 250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
73.3
72.6
dBFS
dBFS
SFDR Spurious Free Dynamic Range at
–25dBFS
Dither “OFF”5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS 30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS 70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS 14 0MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS 250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
100
100
dBFS
dBFS
SFDR Spurious Free Dynamic Range at
–25dBFS
Dither “ON”5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS 30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
l100115
115
dBFS
dBFS 70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
115
115
dBFS
dBFS 140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
110
110
dBFS
dBFS 250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
105
105
dBFS
dBFS
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)
COMMON MODE BIAS CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS
PARAMETER CONDITIONS MIN TYP MAX UNITS
V CM Output Voltage I OUT = 0 1.15
1.25 1.35
V
V CM Output Tempco I OUT = 0
+40ppm/°C
V CM Line Regulation 3.135V ≤ V DD ≤ 3.465V 1mV/ V V CM Output Resistance
1mA ≤ | I OUT | ≤ 1mA
2
Ω
SYMBOL PARAMETER
CONDITIONS MIN
TYP MAX UNITS
ENCODE INPUTS (ENC +, ENC –)
V ID Differential Input Voltage (Note 7)
l
0.2
V
V ICM Common Mode Input Voltage Internally Set
Externally Set (Note 7) 1.2
1.6
3.0
V V R IN Input Resistance (See Figure 2)6k ΩC IN Input Capacitance (Note 7)3
pF LOGIC INPUTS (DITH, PGA, SHDN, RAND)
V IH High Level Input Voltage V DD = 3.3V l 2
V
V IL Low Level Input Voltage V DD = 3.3V l 0.8V I IN Digital Input Current V IN = 0V to V DD l
±10
μA C IN
Digital Input Capacitance
(Note 7)
1.5
pF
LOGIC OUTPUTS (CMOS MODE)
OV DD = 3.3V V OH
High Level Output Voltage
V DD = 3.3V
I O = –10μA I O = –200μA l 3.1
3.2993.29V V V OL
Low Level Output Voltage
V DD = 3.3V I O = 160μA I O = 1.6mA l 0.010.100.4
V V I SOURCE Output Source Current V OUT = 0V –50mA I SINK Output Sink Current V OUT = 3.3V
50mA OV DD = 2.5V V OH High Level Output Voltage V DD = 3.3V , I O = –200μA 2.49V V OL
Low Level Output Voltage V DD = 3.3V , I O = 1.60mA 0.1V OV DD = 1.8V V OH High Level Output Voltage V DD = 3.3V , I O = –200μA 1.79V V OL
Low Level Output Voltage
V DD = 3.3V , I O = 1.60mA
0.1
V
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS V OD Differential Output Voltage 100Ω Differential Load l 247350 454mV V OS
Output Common Mode Voltage 100Ω Differential Load l
1.125 1.2 1.375 V LOW POWER LVDS V OD Differential Output Voltage 100Ω Differential Load l 125175 250mV V OS
Output Common Mode Voltage
100Ω Differential Load
l
1.125
1.2
1.375
V
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T A = 25°C. A IN = –1dBFS. (Note 4)
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)
POWER REQUIREMENTS TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8)l
3.135
3.3 3.465
V P SHDN Shutdown Power SHDN = V DD 0.2
mW
STANDARD LVDS OUTPUT MODE
OV DD Output Supply Voltage (Note 8)
l 3
3.3 3.6V I VDD Analog Supply Current l 440500 mA I OVDD Output Supply Current l 74
90赖特
mA P DIS Power Dissipation l 1647 1950
mW LOW POWER LVDS OUTPUT MODE
OV DD Output Supply Voltage (Note 8)l 3
3.3 3.6V I VDD Analog Supply Current l 440500 mA I OVDD Output Supply Current l 3150 mA P DIS Power Dissipation l
1505
1752mW CMOS OUTPUT MODE
OV DD Output Supply Voltage (Note 8)l 0.5
3.6V I VDD Analog Supply Current l 440500 mA P DIS
Power Dissipation
l
1450
1650
mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f S Sampling Frequency (Note 8)
l 1160MHz t L ENC Low Time Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)l l 2.972.1 3.125 3.12510001000ns ns t H ENC High Time
Duty Cycle Stabilizer Off (Note 7)Duty Cycle Stabilizer On (Note 7)
l l
2.972.1
3.1253.12510001000
ns ns t AP Sample-and-Hold Aperture Delay 1
h5n9ns
LVDS OUTPUT MODE (STANDARD and LOW POWER)
t D ENC to DATA Delay (Note 7)l 1.3 2.5 3.8ns t C ENC to CLKOUT Delay (Note 7)l 1.3 2.5 3.8ns t SKEW DATA to CLKOUT Skew (t C -t D ) (Note 7)
l
–0.6
00.6
ns t RISE Output Rise Time 0.5ns t FALL Output Fall Time 0.5ns Data Latency Data Latency 7
Cycles
CMOS OUTPUT MODE
t D ENC to DATA Delay (Note 7)l 1.3 2.7 4.0ns t C ENC to CLKOUT Delay (Note 7)l 1.3 2.7 4.0ns t SKEW DATA to CLKOUT Skew (t C -t D ) (Note 7)l
–0.6
00.6
ns Data Latency
Data Latency
Full Rate CMOS Demuxed
77
Cycles Cycles
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