digital LC PLL

A Compact Triple-Band Low-Jitter Digital LC PLL

With Programmable Coil in130-nm CMOS

Nicola Da Dalt,Member,IEEE,Edwin Thaller,Peter Gregorius,Associate Member,IEEE,and

Lajos Gazsi,Member,IEEE

Abstract—We present a low-jitter digital LC phase-locked loop (PLL)in a standard digital130-nm CMOS technology,aiming at, but not limited to,clock multiplication in high-speed digital serial interface transceivers.The PLL features a fully digital core and a digitally controlled LC oscillator.The use of an integrated pro-grammable coil enables triple-band operation in multi-GHz range (2.2,3.4,and4.6GHz)on a die area as small as0.21mm2.A new ar-chitecture is proposed which improves the authors’previous work and allows to achieve an outstanding long-term jitter lower than 650fs over the whole frequency range.The PLL consumes13mA of current at1.5-V supply.Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs.Its digital nature makes it easily realizable in the mainstream digital CMOS technologies,robust against noise,and thus ideal for ap-plication as a low-jitter clock multiplying unit in digital intensive systems on chip.

Index Terms—Digital control,digitally controlled oscillator,in-ductors,jitter,phase locked loops.

ext前端框架I.I NTRODUCTION

H IGH-SPEED serial data transceivers in point-to-point

connected systems typically use a phase-locked loop (PLL)as central clock source for a chain of data buffers(see Fig.1).The incoming data stream is re-sampled by a clock and data recovery unit(CDR)and forwarded to the next data buffer. The PLL generates the reference clock for the re-synchroniza-tion unit as well as the core functionality.

Serial data transceivers are traditionally very digital intensive applications,providing a harsh environment to low-noise analog frequency synthesizers.Besides,the design of those blocks is becoming increasingly difﬁcult in the newest deep-submicron technologies,due mainly to decreasing supply voltages and de-terioration of the“analog”performances of transistors.

A digital approach to the implementation of the synthesizer alleviates some of those problems and is also an ideal choice due to its robustness to external noise sources.

A digital architecture for low-bandwidth frequency synthesis has been recently proposed[2].This kind

of architecture cannot be applied to serial data communications where a low-jitter PLL with a bandwidth in the megahertz range is required.In-deed in this case,the quantization noise produced by the digital phase/frequency detection and by the delta-sigma modulator

Manuscript received November12,2004;revised February2,2005.

N.Da Dalt and E.Thaller are with Inﬁneon Technologies Austria AG, Design Center,Development Center Villach,A-9500Villach,Austria(e-mail: nicola.dadalt@inﬁ).

P.Gregorius and L.Gazsi are with Inﬁneon Technologies AG,81669Munich, Germany.

Digital Object Identiﬁer10.1109/JSSC.2005.847325would not be sufﬁciently suppressed by the loop dynamics and would completely spoil the jitter performance of the PLL itself. In this paper,we present a digital approach for high-band-width synthesis based on the bang-bang PLL(BBPLL)principle [3],improving the concept presented in[1].Although most of the high-speed BBPLLs implemented up to now use analog loop ﬁlters,we extend the concept and implement an all-digital ar-chitecture where the only block of analog nature is a digitally controlled LC oscillator.Advantages of this approach include friendly implementation in the newest digital CMOS technolo-gies,improved testability,robustness against PVT variations, low sensitivity to external noise sources,and easy loop

ﬁlter pro-grammability.

An additional motivation for this work is also given by con-siderations on spread-spectrum clocking(SSC).Indeed in most serial transceivers,a frequency modulated clock is used as pri-mary frequency reference to reduce electromagnetic interfer-ence(EMI)[4].Different frequency modulation proﬁles are nor-mally used,like sinusoidal,triangular,or the nonlinear Lexmark modulation proﬁle.The modulation scheme must remain undis-torted through the PLL,to avoid additional deterministic jitter or wander at the CDR sampling point.

Due to the limited bandwidth,analog PLLs with spread-spec-trum input reference clocks exhibit a slight difference between the reference and feedback clock frequencies.As the input spread-spectrum clock frequency migrates from one extreme to the other of the modulation proﬁle,the accumulation of the frequency difference can result in a signiﬁcant amount of phase error within the system.This error will decrease the setup time and hold time margins at the data sampler within the CDR. Especially for systems where the reference clock has to be multiplied,the remaining tracking skew has to be minimized by increasing the closed-loop bandwidth of the PLL.

Apart from the sinusoidal modulation,the commonly applied nonlinear modulation proﬁles contain hig

her order harmonic contents.The maximum frequency change happens when the modulation changes the polarity of its slew rate at the corners. To guarantee a minimum of distortion of all SSC spectral com-ponents,the phase angle of the PLL input-to-output transfer characteristic has to be kept constant within the frequency spec-trum of interest.Due to its nonlinear nature,a properly designed BBPLL can track the SSC achieving less phase distortion than an analog linear PLL.

The synthesizer architecture presented here is not limited to serial data transceivers and can be used as general-purpose clock multiplying unit.

Fig.1.Typical application of the BBPLL.

II.B ANG -B ANG PLL C ONCEPT

A.BBPLL Architecture and Operation

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The block diagram of the implemented BBPLL is shown in Fig.2.A binary phase detector (BPD)detects the phase differ-ence between the reference (Fref)and feedback (Fdiv)clocks,by sampling the reference using the feedback signal.Its oper-ation is functionally equivalent to a sampling register,with the reference connected to the data input and the feedback clock connected to the clock input The output of the BPD is a single bit digital signal having logical value high (if the rising edge of Fref leads that of Fdiv)or low (otherwise).Those logical values can be mapped to num

erical

values 1and 1,respectively.This bit stream is fed to a digital loop ﬁlter (DLF),which con-sists of proportional and integral paths (having

constants

and respectively).The output of the DLF controls the fre-quency of a digitally controlled LC oscillator (DCO)directly without the need of a digital to analog converter.The DCO output signal is divided by a feedback divider (FBD)and the feedback clock (Fdiv)is then used as sampling clock for the BPD and as timing clock for the DLF.

In [8]it has been proven that the ouput jitter of a digital

bang-bang PLL (even of ﬁrst order,that is

with

)in-creases linearly with the DLF latency.For this reason,in this work a different solution than presented in [1]has been used.In particular,instead of adding the proportional and integral paths inside the DLF with a digital adder,this summation is performed electrically inside the DCO.Although this modi ﬁcation seems to be marginal it has indeed a signi ﬁcant impact on the output jitter of the BBPLL,as will be shown in the measurement sec-tion.

Since the BPD is sensitive only to phase information,for fre-quency acquisition an up-down counter (UDC)triggered by the edges of Fref and Fdiv is used.It counts up (down)by 1every-time a falling edg

e of Fref (Fdiv)occurs.In this way its output is actually a measure of the difference between the frequencies of the reference and feedback clocks.This information can be used as frequency detection to accelerate the locking transient of the

BBPLL,by simply scaling it

(constant

)and adding it to the integral path inside the DLF.Note that before being added,it has to be resynchronized inside the loop ﬁlter with the rising edge of Fdiv.

Multistandard support is a desired feature for a synthesizer and target for this work was to cover three different frequency bands,namely 2.2,3.4,and 4.6GHz.Since the tuning range of an integrated

LC oscillator is usually too small to cover the required range,the straightforward solution would have been to place three DCOs on the chip.This approach would entail a big area penalty.Instead,in our solution we cover the three ranges by digitally changing the inductance of the coil of a single DCO with two programming bits.In order to compensate for process variations of the DCO center frequency,the total DCO tuning range is divided into 16equally spaced tuning curves by means of binary-weighted varactors.

The PLL includes also a BIAS stage to generate the currents needed for the DCO and CML prescalers and a JTAG interface for easy test of the module.

Fig.2.BBPLL block diagram.

B.BBPLL Dynamics

In contrast to the traditional charge pump PLLs,which under proper assumptions can be treated as li

near systems,BBPLLs are highly nonlinear systems.The main difference between the two classes is the nature of the phase detector used[6].In stan-dard charge pump PLLs,the output of the phase detector is a pulse-width modulated signal,where the pulsewidth is pro-portional to the phase difference between the reference and the feedback clock.In a BBPLL this phase difference is quantized with one bit resolution.Thus,the BPD introduces a hard nonlin-earity in the loop,invalidating the traditional s-domain analysis used in linear PLLs.

The stability analysis of a digital BBPLL differs from the analysis of analog BBPLLs[3]and can be performed with the aid of nonlinear techniques[7],[8].Assuming a DLF transfer function of the

手机绑定

form

(1)

where is the latency of the DLF integral path measured in

reference clock cycles

and

and the loopﬁlter constants

(Fig.2),then the condition for the BBPLL to be stable is

[8]

(2)

From this expression,the larger the

latency,the larger the

ratio

between

and must be.

If the spread-spectrum technique is used to reduce EMI gen-

erated by the system,the BBPLL must be able to track the fre-

quency modulation applied to the reference clock.Since the

output of the BPD can be

either1or1,the maximum input

frequency modulation amplitude that the proportional path of

the BBPLL can track is limited

to,

where

is the frequency gain of the DCO

and is the feedback di-

vider ratio.If the modulation amplitude exceeds this limit,the

tracking is performed by the integral path.In this case the rate

of change of the feedback clock frequency per clock cycle is

limited

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to.If the rate of change of the reference fre-

quency is bigger than this limit,the BBPLL will go into slew

rate limitation,losing lock.In particular,if the reference clock

frequency is sinusoidally

modulated

(3)

then the maximum frequency rate of change

[Hz/s].Therefore,within one clock cycle the reference

frequency can change

by[Hz]and the

condition for the BBPLL to track it can be written

(4)

imposing a bottom limit on the value

of.It must be noted

that this is a very strict condition,as it assumes a constant slope

in the frequency modulation proﬁle.Since the slope of a sinu-

soidal modulation has the maximum value only around the zero

crossing,a BBPLL which loses momentarily lock around this

point could catch up with the modulation proﬁle a little later,

when the frequency slope has become smaller.

On the other hand,the output jitter of the synthesizer is in-

trinsically limited by the minimum frequency quantization

step

due to the proportional path of the DLF.Since,in case

of a spread-spectrum input clock,a minimum value

for is

enforced by(4),in order to achieve low jitter,the loopﬁlter la-

tency must be kept as small as possible,

and must be

selected to satisfy(2)for stability.

Fig.3.Binary phase detector(BPD).

III.D ESIGN AND I MPLEMENTATION

In this section,some of the building blocks of the BBPLL will be analyzed in more detail.

数字高清网络摄像机In the FBD,two parallel fast prescaler chains are imple-mented,one with TSPC dynamic logic and the other with CML structures to evaluate the impact of the two approaches on the jitter performances of the PLL.The basic structure for all CML blocks is an nMOS differential pair with resistive load.The TSPC latches use the conﬁgurations presented in [9].Measurements on the DCO clock after the prescalers show that there is no appreciable difference in the phase noise be-tween the two different solutions.For operation in the highest frequency band,the TSPC implementation reduces the power consumption of the module by about2mA with respect to the CML implementation.

A CML test multiplexer with simple current steering PECL (pseudo-ECL)output structure using external pull-up resistors is implemented in order to bring the differential output clocks off chip for measurement.In the following,we will concentrate on the most important building blocks of the BBPLL,namely the BPD,the DLF,and the DCO.A.Binary Phase Detector(BPD)

The function of the BPD is to sample the reference clock at the rising edges of the feedback clock.The BPD has a fully differential master–slave structure(see Fig.3).The master and slave latches are identical and are made out of two cross-coupled inverters,whose connection to the power supplies is activated only when the latch is in hold mode.The Fref signal is coupled to the master latch via transmission gates.

Any master–slave register has a tendency to exhibit memory effect in the sampling process.With reference to the present ap-plication,assume that the rising edge of the reference clock(oc-curring at

time)is leading by far the rising edge of the feed-back clock,assumed to beﬁxed at time zero in this example(see Fig.4).In this case the sampled output of the register is high. Now assume that the reference clock edge shifts gradually past the feedback clock edge.Neglecting the effect of thermal noise,

when reaches some threshold

value,the output of the register will switch to low.Due to the memory effect,if the ref-erence edge now shifts back in the opposite direction the tran-sition from low to high will not happen

at but rather at

with.This phenomenon intro-

Fig.4.Illustration of the hysteresis in the binary phase detector.On the left-hand side two cases are depicted:reference edge approaching the divided edge from the left (case 1)and from the right (case 2).The output characteristic of the BPD is illustrated on the right-hand side.

duces a hysteresis in the BPD transfer characteristic,thus in ﬂu-encing negatively the ﬁnal jitter performance of the BBPLL.In order to minimize this effect a nonoverlapping clock generator (NOCL)is used to deliver the sampling clocks for the latches and some delay has been introduced between the master and the slave stages.Simulations have shown that under nominal con-ditions the hysteresis of the comparator is lower than 200fs at 400-MHz clock frequency.B.Digital Loop Filter (DLF)

The DLF consists of proportional and integral paths.The con-

stants

and can assume integer power of two values

programmable in the

ranges

for

and

for (numerical range of the DLF output

to ).The integral path of the DLF is optimized for high-speed and the

latency is equal to 1.5clock cycles (including the DCO latch)for frequencies up to 400MHz.As integrator we use an UP/DOWN counter with selectable bit0position for scaling

of ,and all adders are of the carry-look-ahead type.

The summation of the proportional and the integral paths is done inside the DCO,by digitally switching a small bank of varactors in parallel to the main varactor array of the DCO.In this way,the latency of the loop ﬁlter for the proportional path is reduced to the delay of a few digital gates.

The

constant

for frequency acquisition can be pro-grammed

or .C.LC Digitally Controlled Oscillator (DCO)

The function of the DCO is to generate a clock signal whose

frequency is proportional to the digital code coming from the loop ﬁlter.The block diagram of the implemented DCO is shown in Fig.5.Differently from [10],the LC DCO enables the use of a digital loop ﬁlter without need of a digital to analog converter,thus saving power and area.

The digital control of the frequency is achieved by connecting 1024tiny pMOS varactors in parallel to the tank of an LC oscil-lator.The varactors have dimensions close to the minimum al-lowed by the used technology,resulting in a ﬁne frequency gran-ularity at the output of the DCO and are organized in a squared array of cells.Each cell can be individually set in high or low capacitance state by locally decoding the row and column infor-mation and setting the control voltage of the varactor to digital high or digital low.The 10MSBs of the DLF integral path binary output are converted to thermometer code by two separate

code

Fig.5.Block diagram of the DCO.

converters and then latched to eliminate the output glitches due to different propagation times of the converters.The outputs of the latches provide the row and column information needed to control each individual cell of the array.The two LSBs of the in-tegral path control two binary weighted varactors.The DLF pro-portional path directly controls a small bank of varactors con-nected in parallel to the bigger varactor array.This bank is layout matched to the array,in order to achieve an

accurate

ratio,critical for stability and jitter performances.Special care has to be taken in the layout to minimize the ﬁxed parasitic ca-pacitance of the array.

导热油配方DCO frequency variations due to process are compensated for by using binary weighted varactors (controlled by the bus

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