FEATURES
•Single supply with operation down to 2.5V •Low power CMOS technology - 1 mA active current (typical)
- 1 µ A standby current (maximum)•128 x 8 bit organization (93LC46A)•64 x 16 bit organization (93LC46B)
•Self-timed ERASE and WRITE cycles (including auto-erase)
•Automatic ERAL before WRAL
•Power on/off data protection circuitry •Industry standard 3-wire serial interface
•Device status signal during ERASE/WRITE cycles •Sequential READ function
•1,000,000 E/W cycles guaranteed •Data retention > 200 years
•8-pin PDIP/SOIC and 8-pin TSSOP packages •Available for the following temperature ranges: DESCRIPTION
The Microchip T echnology Inc. 93LC46AX/BX are 1K-bit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP , 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package.
-Commercial (C):0 ° C to +70 ° C -Industrial (I): -40 ° C to +85 °
C
93LC46A/B
1.0ELECTRICAL
CHARACTERISTICS
1.1Maximum Ratings* 7.0V All inputs and Vss ................-0.6V to Vcc +1.0V .-65°C to +150°C Ambient temp. with -65°C to +125°C Soldering temperature of leads (10 seconds).............+300°C ESD protection on 4 kV
带通滤波器*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.TABLE 1-1PIN FUNCTION TABLE Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
NC No Connect
V CC Power Supply
TABLE 1-2DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified operating ranges unless otherwise noted Commercial (C): V CC = +2.5V to +6.0V Tamb = 0°C to +70°C Industrial (I):V CC = +2.5V to +6.0V Tamb = -40°C to +85°C
Parameter Symbol Min.Max.Units Conditions
High level input voltage V IH1 2.0Vcc +1V 2.7V < V CC≤ 5.5V (Note 2) V IH20.7 V CC Vcc +1V V CC < 2.7V
Low level input voltage V IL1-0.30.8V V CC > 2.7V (Note 2) V IL2-0.30.2 Vcc V V CC < 2.7V
Low level output voltage V OL1—0.4V I OL = 2.1 mA; Vcc = 4.5V
V OL2—0.2V I OL =100 µA; Vcc = Vcc Min.
High level output voltage V OH1 2.4—V I OH = -400 µA; Vcc = 4.5V
V OH2V CC-0.2—V I OH = -100 µA; Vcc = Vcc Min.
Input leakage current I LI-1010µA V IN = V SS to Vcc Output leakage current I LO-1010µA V OUT = V SS to Vcc
Pin capacitance (all inputs/outputs)C IN, C OUT—7pF
V IN/V OUT = 0 V (Notes 1 & 2)
Tamb = +25°C, F CLK = 1 MHz
Operating current I CC write— 1.5mA
I CC read
— 1
500
mA
µA
后轮
驱动F CLK = 2 MHz; Vcc = 6.0V
F CLK = 1 MHz; Vcc = 3.0V
Standby current I CCS—1µA CS = Vss
Clock frequency F CLK—2
1
MHz
MHz
V CC > 4.5V
V CC < 4.5V
Clock high time T CKH250—ns
Clock low time T CKL250—ns
Chip select setup time T CSS50—ns Relative to CLK Chip select hold time T CSH0—ns Relative to CLK Chip select low time T CSL250—ns
Data input setup time T DIS100—ns Relative to CLK Data input hold time T DIH100—ns Relative to CLK Data output delay time T PD—400ns C L = 100 pF
Data output disable time T CZ—100ns C L = 100 pF (Note 2) Status valid time T SV—500ns C L = 100 pF
摩根轧机Program cycle time T WC—6ms ERASE/WRITE mode T EC—6ms ERAL mode
T WL—15ms WRAL mode
Endurance—1M—cycles25°C, V CC = 5.0V, Block Mode (Note 3)
Note 1:This parameter is tested at T amb = 25°C and Fclk = 1 MHz.
2:This parameter is periodically sampled and not 100% tested.
3:This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website.
元器件交易网
93LC46A/B
2.0PIN DESCRIPTION
2.1Chip Select (CS)
A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro-gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro-gramming cycle is completed.
CS must be low for 250 ns minimum (T CSL) between consecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.
2.2Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-cation between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH) and clock low time (T CKL). This gives the controlling master freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a ST ART condition).CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a ST ART condition the specified num-ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (T able 2-1 and T able 2-2). CLK and DI then become don't care inputs waiting for a new ST ART condition to be detected.
2.3Data In (DI)
Data In (DI) is used to clock in a ST ART bit, opcode, address, and data synchronously with the CLK input.
2.4Data Out (DO)
Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (T PD after the posi-tive edge of CLK).
This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta-tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T CSL) and an ERASE or WRITE operation has been initiated.
The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.
TABLE 2-1INSTRUCTION SET FOR 93LC46A
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE111A6A5A4A3A2A1A0—(RDY/BSY)10
ERAL10010X X X X X—(RDY/BSY)10
EWDS10000X X X X X—HIGH-Z10
EWEN10011X X X X X—HIGH-Z10
READ110A6A5A4A3A2A1A0—D7 - D018
WRITE101A6A5A4A3A2A1A0D7 - D0(RDY/BSY)18
WRAL10001X X X X X D7 - D0(RDY/BSY)18 TABLE 2-2INSTRUCTION SET FOR 93LC46B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE111A5A4A3A2A1A0—(RDY/BSY)9
ERAL10010X X X X—(RDY/BSY)9
EWDS10000X X X X—HIGH-Z9
EWEN10011X X X X—HIGH-Z9
READ110A5A4A3A2A1A0—D15 - D025
预绞丝WRITE101A5A4A3A2A1A0D15 - D0(RDY/BSY)25
WRAL10001X X X X D15 - D0(RDY/BSY)25
元器件交易网
pet铝膜
93LC46A/B
3.0FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.
3.1START Condition
The ST ART bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.
Before a ST ART condition is detected, CS, CLK, and DI may change in any combination (except to that of a ST ART condition), without resulting in any device oper-ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.
An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new ST ART condition is detected.3.2Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict”to occur during the “dummy z
ero” that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv-ing A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.
3.3Data Protection
During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional pro-tection against accidentally programming during nor-mal operation.
After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
元器件交易网
93LC46A/B
3.4ERASE
The ERASE instruction forces all data bits of the spec-ified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction.3.5Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire ERAL cycle is com-plete.
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