CAT24C256
256-Kb I 2C CMOS Serial EEPROM
PIN CONFIGURATION FUNCTIONAL SYMBOL
FEATURES
■ Supports Standard and Fast I 2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range ■ 64-Byte Page Write Buffer
■ Hardware Write Protection for entire memory ■ Schmitt Triggers and Noise Suppression Filters
on I 2C Bus Inputs (SCL and SDA).
荧光灯支架■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ RoHS compliant
&
■ Industrial temperature range
PDIP (L)SOIC (W)
V CC
V SS
SD A
SCL
WP
A 2, A 1, A 0
DEVICE DESCRIPTION
The CAT24C256 is a 256-Kb Serial CMOS EEPROM, internally organized as 512 pages of 64 bytes each, for a total of 32,768 bytes of 8 bits each.
It features a 64-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I 2C protocol.
Write operations can be inhibited by taking the WP pin High (this protects the entire memory).
The CAT24C256 is available in RoHS compliant “Green” and “Gold” 8-lead PDIP and SOIC packages.
8765
V CC WP SCL SDA
A 2A 0A 1V SS
1234红豆杉提取物
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A 0, A 1, A 2Device Address SDA Serial Data SCL Serial Clock WP Write Protect V CC Power Supply V SS
Ground
* Catalyst carries the I 2C protocol under a license from the Philips Corporation.
CAT24C256
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature-65°C to +150°C Voltage on Any Pin with Respect to Ground(1)-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2)
Symbol Parameter Min Units
N END(*)Endurance1,000,000Program/ Erase Cycles T DR Data Retention100Years
(*) Page Mode, V CC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V CC = 1.8 V to 5.5 V, T A = -40°C to 85°C, unless otherwise specified.
Symbol Parameter Test Conditions Min Max Units
I CC Supply Current Read or Write at 400 kHz1mA
I SB Standby Current All I/O Pins at GND or V CC1μA
I L I/O Pin Leakage Pin at GND or V CC1μA
V IL Input Low Voltage-0.5V CC x 0.3V V IH Input High Voltage V CC x 0.7V CC + 0.5V V OL1Output Low Voltage V CC > 2.5 V, I OL = 3.0 mA0.4V V OL2Output Low Voltage V CC > 1.8 V, I OL = 1.0 mA0.2V
PIN IMPEDANCE CHARACTERISTICS
T A = 25°C, f = 400 kHz, V CC = 5 V
Symbol Parameter Conditions Min Max Units
C IN(2)SDA I/O Pin Capacitance V IN = 0 V8pF
C IN(2)Input Capacitance (other pins)V IN = 0 V6pF
Z WPL WP Input Low Impedance V IN < 0.5 V570kΩ
I LWPH WP Input High Leakage V IN > V CC x 0.71μA Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
CAT24C256
A.C. CHARACTERISTICS
V CC = 1.8 V to 5.5 V, T A = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
1.8 V - 5.5 V
2.5 V - 5.5 V
Units Min Max Min Max
F SCL Clock Frequency100400kHz
T I(1)Noise Suppression Time Constant at
SCL, SDA Inputs
0.10.1μs
改锥头
t AA(2)SCL Low to SDA Data Out 3.50.9μs t BUF(1)Time the Bus Must be Free Before a
New Transmission Can Start
4.7 1.3μs
t HD:STA Start Condition Hold Time40.6μs t LOW Clock Low Period 4.7 1.3μs t HIGH Clock High Period40.6μs t SU:STA Start Condition Setup Time 4.70.6μs t HD:DAT Data In Hold Time00μs t SU:DAT Data In Setup Time0.250.1μs t R(1)SDA and SCL Rise Time10.3μs t F(1)SDA and SCL Fall
Time0.30.3μs t SU:STO Stop Condition Setup Time40.6μs t DH Data Out Hold Time0.10.1μs t WR Write Cycle Time55ms t PU(1), (3)Power-up to Ready Mode11ms Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O
is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of V CC. Output level reference levels are 30% and respectively 70% of V CC.
(3) t PU is the delay required from the time V CC is stable until the device is ready to accept commands.
模具特氟龙
Power-On Reset (POR)
The CAT24C256 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C256 will power up into Standby mode
after V CC exceeds the POR trigger level and will power
膜分离装置down into Reset mode when V CC drops below the POR trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
The POR circuitry triggers at the minimum V CC level
required for proper initialization of the internal state
machines. The POR trigger level automatically tracks the
internal CMOS device thresholds, and is naturally well
below the minimum recommended V CC supply voltage.
CAT24C256
PIN DESCRIPTION
SCL:The Serial Clock input pin accepts the Serial Clock generated by the Master.
SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device ad-dress. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write op-erations, when pulled HIGH. This pin has an on-chip pull-down resistor.
FUNCTIONAL DESCRIPTION
The CAT24C256 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C256 acts as a Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device ad-dress inputs A0, A1, and A2.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the V CC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1).START
The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all receivers. A bsent a START, a Slave will not respond to commands. STOP
The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP starts the internal Write cycle (when follow-ing a Write command) or sends the Slave into standby mode (when following a Read command).
The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write opera-tions (Figure 2). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 3). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 4.
CAT24C256 Figure 1. Start/Stop Timing
Figure 2. Slave Address Bits
Figure 3. Acknowledge Timing
Figure 4. Bus Timing
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