Integrated Circuit
Systems, Inc.
ICS952906A
Recommended Application:
VIA VN800/CN700/P4M800 style chipset for P4 processor Output Features:• 3 - 0.7V current-mode differential CPU pairs •10 - PCI, 3 free running, 33MHz • 2 - REF , 14.318MHz • 3 - 3V66, 66.66MHz • 1 - 48MHz • 1 - 24/48MHz • 2 - 25MHz @ 2.5V Key Specifications:•CPU/SRC outputs cycle-cycle jitter < 125ps •3V66 outputs cycle-cycle jitter < 250ps •PCI outputs cycle-cycle jitter < 250ps •CPU - AGP skew < +/- 350ps •AGP-PCI skew between 1~3.5ns Programmable Timing Control Hub™ for Next Gen P 4™ processor
chdtv
Features/Benefits:
•Programmable output frequency.•Programmable asynchronous 3V66&PCI frequency.•Programmable output divider ratios.•Programmable output skew.•Programmable spread percentage for EMI control.•Watchdog timer technology to reset system if system
malfunctions.•Programmable watch dog safe frequency.•Support I2C Index read/write and block read/write
operations.•Uses external 14.318MHz reference input.
48-pin SSOP & TSSOP
*FS1/REF0148VDDA **FS0/REF1247GND VDDREF 346IREF
X1445CPUCLKT_ITP/(PCI_STOP#)X2544CPUCLKC_ITP/(CPU_STOP#)GND 643GND
**FS2/PCICLK_F0742CPUCLKT1**FS4/PCICLK_F1841CPUCLKC1
对扣PCICLK_F2940VDDCPU
VDDPCI 10
39CPUCLKT0GND 11
38CPUCLKC0**MODE/PCICLK0
1237GND PCICLK113
3525Mhz_1PCICLK315
34VDD2.5PCICLK416
33VttPWR_GD/PD#VDDPCI
1732SDATA GND 18
31SCLK PCICLK519
30Reset#PCICLK6
20293V66_0**FS3/48MHz 21
28GND **Sel24_48#/24_48MHz 2227VDD3V66
GND 23
263V66_1VDD4824
253V66_2* This pin have 120K pull-up to VDD
无人机测量
** This pin have 120K pull-down to GND
I C S 952906
Pin Configuration
Integrated Circuit
Systems, Inc.
ICS952906A
Integrated Circuit
Systems, Inc.
ICS952906A
ICS952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such as the 93788, it provides all the necessary clock signals for such a system.
The ICS952906A is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. E mploying the use of a serially programmable I 2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
Block Diagram
VTTPWRGD#/PD#
FS (4:0)Sel24_48#
MODE
Integrated Circuit
Systems, Inc.
ICS952906A
General I 2C serial interface information for the I CS952906A
How to Write:
•Controller (host) sends a start bit.
•Controller (host) sends the write address D2 (H)•ICS clock will acknowledge
•Controller (host) sends the begining byte location = N •ICS clock will acknowledge
•Controller (host) sends the data byte count = X •ICS clock will acknowledge
•
Controller (host) starts sending Byte N through Byte N + X -1(see Note 2)
•ICS clock will acknowledge each byte one at a time •Controller (host) sends a Stop bit How to Read:
•Controller (host) will send start bit.
•Controller (host) sends the write address D2 (H)•ICS clock will acknowledge
•Controller (host) sends the begining byte location = N
•ICS clock will acknowledge
•Controller (host) will send a separate start bit.•Controller (host) sends the read address D3 (H)•ICS clock will acknowledge
•ICS clock will send the data byte count = X •ICS clock sends Byte N + X -1
•ICS clock sends Byte 0 through byte X (if X (H)was written to byte 8).
•Controller (host) will need to acknowledge each byte •Controllor (host) will send a not acknowledge bit •
Controller (host) will send a stop bit
Integrated Circuit
Systems, Inc.
ICS952906A
Integrated Circuit
Systems, Inc.
ICS952906A
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