TPA3116D2TPA3118D2TPA3130D2
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SLOS708B –APRIL 2012–REVISED MAY 2012
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance
Check for Samples:TPA3116D2,TPA3118D2,TPA3130D2
FEATURES
电极臂
DESCRIPTION
The TPA31xxD2series are stereo efficient,digital •
Supports Multiple Output Configurations amplifier power stage for driving speakers up to –2×50-W into a 4-ΩBTL Load at 21V 100W/2Ωin mono.The high efficiency of the (TPA3116D2)
TPA3130D2allows it to do 2x15W without external –2×30-W into a 8-ΩBTL Load at 24V heat sink on a single layer PCB.The TPA3118D2can even run 2x30W/8Ωwithout heat sink on a dual layer (TPA3118D
2)
PCB.If even higher power is needed the TPA3116D2–2×15-W into a 8-ΩBTL Load at 15V does 2x50W/4Ωwith a small heat-sink attached to its (TPA3130D2)
top side PowerPad.All three devices share the same •Wide Voltage Range:4.5V –26V footprint enabling a single PCB to be used across different power levels.
•
Efficient Class-D Operation
–>90%Power Efficiency Combined with Low The TPA31xxD2advanced oscillator/PLL circuit Idle Loss Greatly Reduces Heat Sink Size employs a multiple switching frequency option to avoid AM interferences;this is achieved together with –Advanced Modulation Schemes an option of Master/Slave option,making it possible •
Multiple Switching Frequencies to synchronize multiple devices.
–AM Avoidance
The TPA31xxD2devices are fully protected against –Master/Slave Synchronization
faults with short-circuit protection and thermal –Up to 1.2MHz Switching Frequency
protection as well as over-voltage,under-voltage and DC protection.Faults are reported back to the •Feedback Power Stage Architecture with High processor to prevent devices from being damaged PSRR Reduces PSU Requirements during overload conditions.
•Programmable Power Limit
•Differential/Single-Ended Inputs
Simplified Application Circuit
•Stereo and Mono Mode with Single Filter Mono Configuration
•Single Power Supply Reduces Component Count
•
Integrated Self-Protection Circuits Including Over-Voltage,Under-Voltage,Over-Temperature,DC-Detect,and Short Circuit with Error Reporting
•
Thermally Enhanced Packages –DAD (32-pin HTSSOP Pad-up)DEVICE POWER HTSSOP 32-PIN –DAP (32-pin HTSSOP Pad-down)
TPA3130D22x 15W/8ΩPad down (DAP)•
–40°C to 85°C Ambient Temperature Range
TPA3118D22x 30W/8ΩPad down (DAP)TPA3116D2机械原理模型 2x 50W/4Ω
Pad up (DAD)
APPLICATIONS
•Mini-Micro Component,Speaker Bar,Docks •After-Market Automotive •CRT TV
•
Consumer Audio Applications
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PACKAGE (TOP VIEW)
FAULTZ SDZ SYNC
AM0AM1MUTE LINN LINP PLIMIT RINN GVDD RINP AVCC
OUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSEL
BSPR GND GND PVCC GND GAIN/SLV
AM2PACKAGE (TOP VIEW)
FAULTZ SDZ SYNC
AM0AM1MUTE LINN LINP PLIMIT RINN GVDD RINP AVCC
OUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSEL
BSPR GND GND PVCC GND GAIN/SLV
AM2TPA3116D2TPA3118D2TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti
These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL ASSIGNMENT
TPA3116D2
TPA3130D2and TPA3118D232-PIN HTSSOP PACKAGE (DAD)
32-PIN HTSSOP PACKAGE (DAP)
Terminal Functions
PIN
TYPE (1)
DESCRIPTION
NO.NAME 1MODSEL I Mode selection logic input (LOW =BD mode,HIGH =1SPW mode).TTL logic levels with compliance to AVCC.
2SDZ I Shutdown logic input for audio amp (LOW =outputs Hi-Z,HIGH =outputs enabled).TTL logic levels with compliance to AVCC.
3
FAULTZ
DO
General fault reporting including Over-temp,DC Detect.Open drain.FAULTZ =High,normal operation
FAULTZ =Low,fault condition
4RINP I Positive audio input for right channel.Biased at 3V.5RINN I Negative audio input for right channel.Biased at 3V.
6PLIMIT I Power limit level adjust.Connect a resistor divider from GVDD to GND to set power limit.Connect directly to GVDD for no power limit.
7GVDD PO Internally generated gate voltage supply.Not to be used as a supply or connected to any component other than a 1µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.8GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.9GND G Ground
10LINP I Positive audio input for left channel.Biased at 3V.Connect to GND for PBTL mode.11LINN I Negative audio input for left channel.Biased at 3V.Connect to GND for PBTL mode.
12MUTE I Mute signal for fast disable/enable of outputs (HIGH =outputs Hi-Z,LOW =outputs enabled).TTL logic levels with compliance to AVCC.13AM2I AM Avoidance Frequency Selection 14AM1
I
AM Avoidance Frequency Selection
(1)TYPE :DO =Digital Output,I =Analog Input,G =General Ground,PO =Power Output,BST =Boot Strap.
TPA3116D2
TPA3118D2
TPA3130D2 www.ti SLOS708B–APRIL2012–REVISED MAY2012
Terminal Functions(continued)
PIN
TYPE(1)DESCRIPTION
NO.NAME
15AM0I AM Avoidance Frequency Selection
16SYNC DIO Clock input/output for synchronizing multiple class-D devices.Direction determined by GAIN/SLV terminal. 17AVCC P Analog Supply
18PVCC P Power supply
19PVCC P Power supply
镭射贴20BSNL BST Boot strap for negative left channel output,connect to220nF X5R,or better ceramic cap to OUTPL
21OUTNL PO Negative left channel output
22GND G Ground
23OUTPL PO Positive left channel output
24BSPL BST Boot strap for positive left channel output,connect to220nF X5R,or better ceramic cap to OUTNL
25GND G Ground
26BSNR BST Boot strap for negative right channel output,connect to220nF X5R,or better ceramic cap to OUTNR
27OUTNR PO Negative right channel output
28GND G Ground
29OUTPR PO Positive right channel output
30BSPR BST Boot strap for positive right channel output,connect to220nF X5R or better ceramic cap to OUTPR
31PVCC P Power supply
32PVCC P Power supply
33Thermal Pad G Connect to GND for best system performance.If not connected to GND,leave floating.
or
PowerPAD
SDZ GAIN
RINP RINN
FAULTZ
AVCC
GVDD
LINN LINP
GND
OUTPL
BSPL
GND
OUTNL
GND
GND
BSPR
Pad
TPA3116D2TPA3118D2TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti
SYSTEM BLOCK DIAGRAM
TPA3116D2
TPA3118D2
TPA3130D2 www.ti SLOS708B–APRIL2012–REVISED MAY2012 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range(unless otherwise noted)(1)
VALUE UNIT Supply voltage,V CC PV CC,AV CC–0.3to30V
INPL,INNL,INPR,INNR–0.3to6.3V Input voltage,V I PLIMIT,GAIN/SLV,SYNC–0.3to GVDD+0.3V
AM0,AM1,AM2,MUTE,SDZ,MODSEL–0.3to PVCC+0.3V Slew rate,maximum(2)AM0,AM1,AM2,MUTE,SDZ,MODSEL10V/msec Operating free-air temperature,T A–40to85°C Operating junction temperature range,T J–40to150°C Storage temperature range,T stg–40to125°C Electrostatic discharge:Human body model,ESD±2kV Electrostatic discharge:Charged device model,ESD±500V (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)100kΩseries resistor is needed if maximum slew rate is exceeded.
THERMAL INFORMATION
TPA3130D2TPA3118D2TPA3116D2
DAP DAP DAD
THERMAL METRIC(1)UNITS
1Layer PCB(2)2Layer PCB(3)Heatsink(4)
32PINS32PINS32PINS
θJA Junction-to-ambient thermal resistance362214
滚花铜螺母ψJT Junction-to-top characterization parameter0.40.3 1.2°C/W ψJB Junction-to-board characterization parameter 5.9 4.8 5.7
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
(2)For the PCB layout please see the TPA3130D2EVM user guide.A1layer90x85mm1oc PCB was used
(3)For the PCB layout please see the TPA3130D2EVM user guide.A2layer90x85mm1oc PCB was used
(4)The heat sink drawing used for the thermal model data are shown in the application section,size:14mm wide,50mm long,25mm high. RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range(unless otherwise noted)
MIN NOM MAX UNIT V CC Supply voltage PV CC,AV CC 4.526V果蔬气调库
High-level input
V IH AM0,AM1,AM2,MUTE,SDZ,SYNC,MODSEL2V voltage
Low-level input
V IL AM0,AM1,AM2,MUTE,SDZ,SYNC,MODSEL0.8V voltage
Low-level output
V OL FAULTZ,R PULL-UP=100kΩ,PV CC=26V0.8V voltage
High-level input
I IH AM0,AM1,AM2,MUTE,SDZ,MODSEL(V I=2V,V CC=18V)50µA
current
TPA3116D2,TPA3118D2 3.24
R L(BTL)Output filter:L=10µH,C=680nF
TPA3130D2 5.68 Minimum load
ΩImpedance TPA3116D2,TPA3118D2 1.6
R L(PBTL)Output filter:L=10µH,C=1µF
TPA3130D2 3.24
Output-filter
L o Minimum output filter inductance under short-circuit condition1µH Inductance
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