非安全Tables 4–98 through 4–105 show the maximum DCD in absolution
derivation for different I/O standards on Stratix II GX devices. Examples
涤绒
are also provided that show how to calculate DCD as a percentage.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95ps (see Table 4–99). If the clock frequency is 267MHz, the clock
period T is:
T = 1/ f = 1 / 267MHz = 3.745ns = 3,745ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745ps/2 – 95ps) / 3,745ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3,745ps/2 + 95ps) / 3,745ps = 52.5% (for high
boundary)
Table 4–98.Maximum DCD for Non-DDIO Output on Row I/O Pins
Row I/O Output Standard
Maximum DCD (ps) for Non-DDIO Output -3 Devices -4 and -5 Devices Unit 3.3-V LVTTTL
245275ps 3.3-V LVCMOS
125155ps 2.5 V
105135ps 1.8 V
180180ps 1.5-V LVCMOS
165195ps SSTL-2 Class I
115145ps SSTL-2 Class II
95125ps SSTL-18 Class I
5585ps 1.8-V HSTL Class I
80100ps 1.5-V HSTL Class I
85115ps LVDS 5580ps
Table4–100.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Note(1)
Maximum DCD (ps) for Row DDIO Output I/O
Input I/O Standard (No PLL in Clock Path)
Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS
3.3 and
2.5 V
1.8 and
1.5 V
2.5 V
1.8 and
1.5 V
3.3 V
3.3-V LVTTL260380145145110ps 3.3-V LVCMOS21033010010065ps 2.5 V195315858575ps 1.8 V1502658585120ps 1.5-V LVCMOS255370140140105ps SSTL-2 Class I175295656570ps SSTL-2 Class II170290606075ps SSTL-18 Class I155275555090ps 1.8-V HSTL Class I150270606095ps 1.5-V HSTL Class I150270555590ps LVDS180180180180180ps
Therefore, the DCD percentage for the output clock is from 48.4% to
51.6%.
Table4–101.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note(1)
Maximum DCD (ps) for Row DDIO Output I/O
Standard
Input I/O Standard (No PLL in the Clock Path)
Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS
3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3V
3.3-V LVTTL440495170160105ps 3.3-V LVCMOS39045012011075ps 2.5 V3754301059590ps 1.8 V32538590100135ps 1.5-V LVCMOS430490160155100ps SSTL-2 Class I355410857585ps SSTL-2 Class II350405807090ps SSTL-18 Class I3353906565105ps 1.8-V HSTL Class I3303856070110ps 1.5-V HSTL Class I3303906070105ps LVDS180180180180180ps
(1)Table4–101 assumes the input clock has zero DCD.
Table4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of2)Note(1)
三角形算法Maximum DCD (ps) for DDIO Column Output I/O Standard
Input IO Standard (No PLL in the Clock Path)
Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL12
3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V
3.3-V LVTTL260380145145145ps 3.3-V LVCMOS210330100100100ps 2.5 V195315858585ps 1.8 V150265858585ps 1.5-V LVCMOS255370140140140ps SSTL-2 Class I175295656565ps SSTL-2 Class II170290606060ps SSTL-18 Class I155275555050ps
SSTL-18 Class II
140260707070ps 1.8-V HSTL Class I
150270606060ps 1.8-V HSTL Class II
150270606060ps 1.5-V HSTL Class I
150270555555ps 1.5-V HSTL Class II
125240858585ps 1.2-V HSTL
240360155155155ps LVPECL 180180180180180ps
(1)Table 4–102 assumes the input clock has zero DCD.
Table 4–103.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note (1)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
圣诞工艺品Input IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3-V LVTTL
440495170160ps 3.3-V LVCMOS
390450120110ps 2.5 V
37543010595ps 1.8 V
32538590100ps 1.5-V LVCMOS
430490160155ps SSTL-2 Class I
3554108575ps SSTL-2 Class II
3504058070ps SSTL-18 Class I
3353906565ps SSTL-18 Class II
3203757080ps 1.8-V HSTL Class I
3303856070ps 1.8-V HSTL Class II
3303856070ps 1.5-V HSTL Class I
3303906070ps 1.5-V HSTL Class II
33036090100ps LVPECL
180180180180ps (1)Table 4–103 assumes the input clock has zero DCD.Table 4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 2 of 2) Note (1)
Maximum DCD (ps) for
电子差速器
DDIO Column Output I/O Standard
Input IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL123.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V
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