Data sheet
Issue No : PD-701-028
1/4 inch VGA class Analog/Digital Output
NTSC/PAL CMOS Image Sensor
PC1030N
R 10Rev 1.0
Last update : 22 . Sep. 2009
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,
Suwon-si, Gyeonggi-do, 443-766, Korea Tel : 82-31-888-5300, FAX : 82-31-888-5398
Copyright ⓒ2009, Pixelplus Co.,Ltd py g ,p ,
ALL RIGHTS RESERVED
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1/4i h VGA l A l /Di it l O t t
1/4 inch VGA class Analog/Digital Output NTSC/PAL CMOS Image Sensor
▶Revision History
Date [D/M/Y]Version Date [D/M/Y]Notes
Writer 0.020/05/2008(Preliminary)
Jong Beom Choi 0.104/06/2008Customer datasheet is released SungJe Cheon
0.2
20/06/2008
DVDD voltage is modified SungJe Cheon Add DC Characteristics
Add AC Ch t i ti 0.304/07/2008
Add AC Characteristics Add Optical Performance Add Power Sequence
Junhee Cho 0.409/07/2008Modify effective pixel area. Fig.10SungJe Cheon 0.522/07/2008Modify LED Control
Bongju Lee 06Add VGA di it l t t l d S J Ch 0.628/07/2008Add VGA digital output only mode SungJe Cheon 0.723/09/2008Removed “Preliminary” letters
Jincheol Jeong 0.806/02/2009Released Power Sequence
Yoon Shik Kim 0.927/03/2009Change (Total pixel array ÆEffective pixel array)
Heungseok Park Add Application note Jongwu Ryu 1.0
21/05/2009
Add Application note
Jongwu Ryu 1.122/09/2009
Change(SCLK ÆSSCLK, SDAT ÆSSDAT,
RCLK ÆRSCLK, RDAT ÆRSDAT) Page 7,20,29,30
Modify Fig number. Page 13,14,15,18,19
JiKyung Moon
Caution : This datasheet can be changed without prior notice !! If you want to get up-to-date version,
please send a mail to kr.C
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1/4i h VGA l A l /Di it l O t t
1/4 inch VGA class Analog/Digital Output NTSC/PAL CMOS Image Sensor
▶Table of Contents
(3)640x480VGA Digital Output Only ▶Features
pet打包带
生产线-[ Fig. 1 ] PIN Description -[ Table 1 ] Typical Parameters▶Pin Descriptions
(3) 640x480 VGA Digital Output Only -[Fig.10] Timing diagram for Hsync, MCLK,
PCLK and Data ( Default : YUV )
-[Fig.11] Timing diagram for Hsync, MCLK,
PCLK and Data ( Bayer )
-[ Table 2 ] Pin Descriptions
▶Signal Environment
▶Chip Architecture -[Fig.12] Timing diagram for Vsync and Hsync
▶NTSC/PAL wire-strapping -[Fig 13]Example of wire-strapping -[Table 3]wire-strapping
自制室内单杠p -[ Fig. 2 ] Block Diagram ▶Frame Structure and Windowing
-[ Fig. 3 ] Default data structure of frame and -[Table 4]TV mode registers -[Table 5]Flicker mode register -[Table 6]Mirror mode register ▶Register initializing by I2C EEPROM window
▶Data Formats
-[ Fig. 4 ] Bayer Color Filter Pattern
-[ Fig. 5 ] 4:2:2 YUV data sequence.
-[Fig 14]Connection with I2C EEPROM -[Fig 15]Configuration of I2C EEPROM
▶2-wire Serial Interface Description
▶Data and Synchronization Timing
(1) ITU-R BT656
-[ Fig. 6 ] Timing diagram of ITU-R BT601 and
ITU-R BT656.
▶2-wire Serial Interface Functional Description
▶Register Tables
Register Tables ( Detailed ) -[ Fig. 7 ] Vertical Timing diagram of ITU-R of
ITU-R BT656.
(2) 320x240 (320x288) Digital Output -[ Fig. 8 ] Timing diagram for Hsync, MCLK,
PCLK and Data -[Fig 9]Timing diagram for Vsync and Hsync
▶g ()
▶Application Note
[ Fig. 9 ] Timing diagram for Vsync and Hsync.C
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1/4i h VGA l A l /Di it l O t t
1/4 inch VGA class Analog/Digital Output NTSC/PAL CMOS Image Sensor
▶Features
▷648 x 488 Effective pixel array with R S D A T L E D C T L 1H V D D H G N D D G N D D V D D C A D D R 1C A D D R 0M O T I O N L E D C T L 0RGB bayer color filters and micro-lens and optical black pixel.▷Power supply :
AVDD : 2.8V, CVDD : 2.8V, DVDD : 1.8V,HVDD : 2.8 ~ 3.3V
PCLK X2X1D3D2D1RSCLK SSCLK SSDAT
D4D5HSYNC
3637383940125242322212035 34 33 32 31 30 29 28 27 26
▷Output formats :
CVBS ( NTSC/PAL),
ITU-R. BT601/656( 60 fields/sec. interlaced @ 27MHz) with CVBS,
320x240(288) YCbCr422 (30(25)fps. @ 27MHz)with CVBS D C C D Y D P N 11
D0TE REXT CGND
D6D7VSYNC RSTB
PC1030N
2345
6 7 8 9 10 11 12 13 14 15
19181716
with CVBS,
640x480(VGA) YCbCr422 digital output only (30fps. @ 27MHz).
▷Image processing on chip :
lens shading, gamma correction, defect correction, low pass filter,
[ Fig. 1 ] PIN Description (CLCC)
A V D N N A G N S T D
C V
D C C A V D D A G N D color interpolation, edge enhancement, color correction, brightness, contrast,
saturation, auto black level compensation, auto white balance, auto exposure control and back light compensation.
Frame size window size and position can Optical Format ¼ inch
Pixel Size
5.55 um x 5.55 um Effective Pixel Array 648 x 488
Effective Image Area 3596.4um x 2708.4um Clock Frequency 27MHz ▷Frame size, window size and position can be programmed through a 2-wire serial interface bus.
▷VGA / QVGA / QQVGA / CIF / QCIF Scaling.
50Hz 60Hz flicker automatic cancellation Clock Frequency 27 MHz
rfid标签生产Frame Rate 60(50) fields/sec @ 27MHz Dark Signal 47.9 [mV/sec] @60’C Sensitivity
3.16 [V/Lux.sec]213 [mW] @ Dynamic ▷50Hz, 60Hz flicker automatic cancellation.▷High Image Quality and High low light performance.
Power Consumption []@y 19.2 [uW] @ Standby Operating Temp.
(Fully Functional Temp.)-40’C ~ 105’C Dynamic Range 63.5 [dB] @60’C [ Table 1 ] Typical Parameters
SNR
45.6 [dB] @60’C
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1/4i h VGA l A l /Di it l O t t
1/4 inch VGA class Analog/Digital Output NTSC/PAL CMOS Image Sensor
▶PIN Descriptions
[ Table 2 ] Pin Descriptions
PIN N Name I/O
T Functions / Descriptions
No.Type 1HSYNC O Horizontal synchronization pulse. HSYNC is high ( or low ) for the horizontal window of
interest. It can be programmed to appear or not outside the vertical window of interest.
2D6O Bit 6 of parallel data output.
3D7O Bit 7 of parallel data output.c型变压器
4VSYNC O Vertical sync : Indicates the start of a new frame.y
5RSTB I System reset must remain low for at least 8 master clocks after power is stabilized. When the sensor is reset, all registers are set to their default values.6AVDD P
Analog Power supply : 2.8V DC with 0.1uF capacitor to AGND.
7N.C 8N.C 9AGND P Analog Power ground
10
STDBY
I Power standby mode. When STDBY=‘1’ there’s no current flow in any analog circuit branch, neither any beat of digital clock. D<9:0> and PCLK, HSYNC, VSYNC pins can be programmed to tri-state or all ‘1’ or all ‘0’. But it is possible to control internal registers through I2C bus interface in STDBY mode. All registers retain their current values.11CVDD P DAC Power supply : 2.8V DC with 0.1uF capacitor to AGND.Composite signal (Connect to 75ohm to AGND)12CP O Composite signal. (Connect to 75ohm to AGND)
13CN O Connect 37.5ohm to AGND 14AVDD1
P
Analog Power supply : 2.8V DC with 0.1uF capacitor to AGND.
15AGND1P Analog Power ground 16CGND P DAC Power ground.17REXT I External Resistor. The resistor value can be changed by user tuning. (Connect to 30Kohm to AGND)
18TE
I
Chip Test Mode enable. (Connect to HGND)
19D0O Bit 0 of parallel data output.20D1
O Bit 1 of parallel data output.Bit 2of parallel data output 21
D2O Bit 2 of parallel data output.22D3O Bit 3 of parallel data output.23X1I Master clock input pad or Crystal input pad
24X2O Crystal output pad
25PCLK O Pixel clock. Data can be latched by external devices at the rising or falling edge of PCLK. The polarity and drivability can be controlled.
26
LEDCTRL0
O
LED Control bit 0. LEDCTRL[1:0] provide 2bit combination of enable signal which can turn-on LED device when low light condition.
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