盖型螺母Low Power Stereo Audio CODEC
With Headphone Amplifier
ES8328 GENERAL DESCRIPTION FEATURES
ES8328 is a high performance, low power and low cost audio CODEC. It consists of 2-ch ADC, 2-ch DAC, microphone amplifier, headphone amplifier, digital sound effects, and analog mixing and gain functions.
The device uses advanced multi-bit delta-sigma modulation technique to convert data between digital and analog. The multi-bit delta-sigma modulators make the device with low sensitivity to clock jitter and low out of band noise. ADC
• 24-bit, 8 kHz to 96 kHz sampling frequency
• 95 dB dynamic range, 95 dB signal to noise ratio, -85 dB THD+N
• Stereo or mono microphone interface with microphone amplifier
• Auto level control and noise gate
• 3-to-1 analog input selection
• Various analog input mixing and gains
DAC
• 24-bit, 8 kHz to 96 kHz sampling frequency
• 96 dB dynamic range, 96 dB signal to noise ratio, -83 dB THD+N
• 40 mW headphone amplifier, pop noise free, capless option
• Stereo enhancement
• Bass and Treble
• Various analog output mixing and gains
Low Power
• 1.8V to 3.3V operation
• 7 mW playback; 16 mW playback and record System
• I2C or SPI uC interface
• 256Fs, 384Fs, USB 12 MHz or 24 MHz
• Master or slave serial port
• I2S, Left Justified, DSP/PCM Mode
APPLICATIONS
ORDERING
INFORMATION
• GPS
• Bluetooth
• MP3, MP4, PMP
• Cell phone
• Digital camera, camcorder • Portable audio devices ES8328 -40°C ~ +85°C
QFN-28
1 BLOCK DIAGRAM (4)
2 28-PIN QFN AND PIN DESCRIPTIONS (5)
3 TYPICAL APPLICATION CIRCUIT (7)
4 CLOCK MODES AND SAMPLING FREQUENCIES (7)
5 MICRO-CONTROLLER CONFIGURATION INTERFACE (9)
5.1 SPI (9)
5.2 2-wire (10)
6 CONFIGURATION REGISTER DEFINITION (11)
6.1 Chip Control and Power Management (12)
6.1.1 Register 0 – Chip Control 1, Default 0000 0110 (12)
6.1.2 Register 1 – Chip Control 2, Default 0001 1100 (13)
6.1.3 Register 2 – Chip Power Management, Default 1100 0011 (13)
6.1.4 Register 3 – ADC Power Management, Default 1111 1100 (14)
6.1.5 Register 4 – DAC Power Management, Default 1100 0000 (14)
6.1.6 Register 5 – Chip Low Power 1, Default 0000 0000 (15)
6.1.7 Register 6 – Chip Low Power 2, Default 0000 0000 (15)
6.1.8 Register 7 – Analog Voltage Management, Default 0111 1100 (16)
6.1.9 Register 8 – Master Mode Control, Default 1000 0000 (16)
6.2 ADC Control (16)
6.2.1 Register 9 – ADC Control 1, Default 0000 0000 (16)
6.2.2 Register 10 – ADC Control 2, Default 0000 0000 (16)
6.2.3 Register 11 – ADC Control 3, Default 0000 0110 (17)
6.2.4 Register 12 – ADC Control 4, Default 0000 0000 (17)
6.2.5 Register 13 – ADC Control 5, Default 0000 0110 (18)
6.2.6 Register 14 – ADC Control 6, Default 0011 0000 (18)
6.2.7 Register 15 – ADC Control 7, Default 0011 0000 (18)
6.2.8 Register 16 – ADC Control 8, Default 1100 0000 (19)
6.2.9 Register 17 – ADC Control 9, Default 1100 0000 (19)
6.2.10 Register 18 – ADC Control 10, Default 0011 1000 (19)
6.2.11 Register 19 – ADC Control 11, Default 1011 0000 (20)
6.2.12 Register 20 – ADC Control 12, Default 0011 0010 (20)
6.2.13 Register 21 – ADC Control 13, Default 0000 0110 (21)
6.2.14 Register 22 – ADC Control 14, Default 0000 0000 (21)
6.3 DAC Control (21)
6.3.1 Register 23 – DAC Control 1, Default 0000 0000 (21)
6.3.2 Register 24 – DAC Control 2, Default 0000 0110 (22)
6.3.3 Register 25 – DAC Control 3, Default 0011 0010 (22)
6.3.4 Register 26 – DAC Control 4, Default 1100 0000 (23)
6.3.5 Register 27 – DAC Control 5, Default 1100 0000 (23)
6.3.6 Register 28 – DAC Control 6, Default 0000 1000 (23)
6.3.7 Register 29 – DAC Control 7, Default 0000 0110 (23)
6.3.8 Register 30 – DAC Control 8, Default 0001 1111 (24)
6.3.9 Register 31 – DAC Control 9, Default 1111 0111 (24)
6.3.10 Register 32 – DAC Control 10, Default 1111 1101 (24)
6.3.11 Register 33 – DAC Control 11, Default 1111 1111 (24)
6.3.12 Register 34 – DAC Control 12, Default 0001 1111 (24)
6.3.13 Register 35 – DAC Control 13, Default 1111 0111 (24)
6.3.14 Register 36 – DAC Control 14, Default 1111 1101 (25)
6.3.15 Register 37 – DAC Control 15, Default 1111 1111 (25)
6.3.16 Register 38 – DAC Control 16, Default 0000 0000 (25)
6.3.17 Register 39 – DAC Control 17, Default 0011 1000 (25)
6.3.18 Register 40 – DAC Control 18, Default 0011 1000 (25)
6.3.19 Register 41 – DAC Control 19, Default 0011 1000 (26)
6.3.20 Register 42 – DAC Control 20, Default 0011 1000 (26)
6.3.21 Register 43 – DAC Control 21, Default 0011 1000 (27)
6.3.22 Register 44 – DAC Control 22, Default 0011 1000 (27)
6.3.23 Register 45 – DAC Control 23, Default 0000 0000 (27)
6.3.24 Register 46 – DAC Control 24, Default 0000 0000 (28)
6.3.25 Register 47 – DAC Control 25, Default 0000 0000 (28)
6.3.26 Register 48 – DAC Control 26, Default 0000 0000 (28)
6.3.27 Register 49 – DAC Control 27, Default 0000 0000 (29)
6.3.28 Register 50 – DAC Control 28, Default 0000 0000 (29)
6.3.29 Register 51 – DAC Control 29, Default 0000 0000 (29)
6.3.30 Register 52 – DAC Control 30, Default 0000 0000 (29)
7 Digital Audio Interface (30)
8 ELECTRICAL CHARACTERISTICS (31)
8.1 Absolute Maximum Ratings (31)
8.2 Recommended Operating Conditions (31)
8.3 ADC Analog and Filter Characteristics and Specifications (31)
8.4 DAC Analog and Filter Characteristics and Specifications (32)
8.5 Power Consumption Characteristics (33)
8.6 Serial Audio Port Switching Specifications (33)
8.7 Serial Control Port Switching Specifications (34)
9 PACKAGE INFORMATION (36)
ostasksuspend
INFORMATION (37)
10 CORPOARATION
ALRCK ASDOUT DLRCK DSDIN SCLK
CE CCLK CDATA MCLK LIN1 LIN2 LOUT1ROUT1
LOUT2ROUT2
RIN1 RIN2
2 28-PIN QFN AND PIN DESCRIPTIONS
C C L K
C D A T A C E
多功能限位器A D C V R E F
L I N 1
R I N 1 L I N 2
1 2 3 4 5 6
7
28
27
26
25
24
23
22 21201918171615
8 9
10
11
12
13
14
MCLK DVDD PVDD DGND SCLK DSDIN
DLRCK RIN2 VMID DACVREF AGND AVDD HPVDD LOUT2
A S D O U T
A L R C K
O U T 3
R O U T 1
L O U T 1
H P G N D
R O U T 2
ES8328 is pin compatible to WM8988 except the yellow highlighted pins in the following table.
p612
PIN NAME I/O DESCRIPTION
clock
1 MCLK I Master
2 DVDD Supply Digital core supply镇流器外壳
3 PVDD Supply Digital IO supply
4 DGND Supply Digital ground (return path for both DVDD and PVDD)
5 SCLK I/O Audio data bit clock
6 DSDIN I DAC audio data
7 DLRCK I/O DAC audio data left and right clock
8 ASDOUT O ADC audio data
9 ALRCK I/O ADC audio data left and right clock (can be NC in master mode)
10 OUT3 O Used for capless headphone option
11 ROUT1 O Right output 1 (line or speaker/headphone)
12 LOUT1 O Left output 1 (line or speaker/headphone)
13 HPGND Supply Ground for analog output drivers (LOUT1/2, ROUT1/2)
14 ROUT2 O Right output 2 (line or speaker/headphone)
15 LOUT2 O Left output 2 (line or speaker/headphone)
16 HPVDD Supply Supply for analog output drivers (LOUT1/2, ROUT1/2)
supply
17 AVDD Supply Analog
ground
18 AGND Supply Analog
19 ADCVREF O Decoupling
capacitor
capacitor
20 VMID O Decoupling
21 RIN2 AI Right channel input 2
22 LIN2 I Left channel input 2
23 RIN1 I Right channel input 1
24 LIN1 I Left channel input 1
25 DACREF 0 Decoupling capacitor
26 CE I Control select or device address selection
27 CDATA I/O Control data input or output
28 CCLK I Control clock input
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