CMOS全加器
课程设计报告
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A、B分别为加数与被加数，Ci为低位向本位的进位值，S为“和”，Co为本位向高位的进位值。全加器的逻辑关系为：S=A⊕B⊕Ci 卡孔 Co=ACi+BCi+AB=(A⊕B)Ci+AB
全加器真值表：
A B Ci | S Co | A B Ci | S Co |
0 0 0 | 0 0 | 1 0 0 | 1 0 |
0 0 1 | 1 0 | 1 0 1 | 0 1 |
0 1 0 | 1 0 | 1 1 0 | 0 1 |
0 1 1 | 0 1 | 1 1 1 | 1 0 |
| | | |
二、电路结构的设计
该电路传输门1与反相器构成异或门，传输门2与反相器构成同或门，其输出分别为A⊕B、。同或门与异或门的关系为：只要将异或门的输出端反相，如A变成，那么异或门就变成了同或门，反之亦然。该电路实现全加器的原理为：
因为
S= A⊕B⊕Ci=( A⊕B)+（）Ci
当=0，A⊕B=1时，S=
当=1，A⊕B=0时，S= Ci
因此，求和只需用一个2选1数据选择器，用A⊕B和作为控制信号，用Ci与作为输入信号即可。 图中传输门3和4组成2选1数据选择器。
进位信号：Co=( A⊕B) Ci+AB
当A⊕B=0，则A=B=1 Co=1=A=B ， A=B=0 Co=0=A=B，即Co选择A或B。
当A⊕B=1，则AB，Co=Ci，即Co选择Ci。
因此，同样用一个2选1电路，用A⊕B和作为控制信号，Co在A和Ci选择。图中传输门5和6构成2选1电路，完成进位信号输出功能。输出端反相器一方面可以增加驱动能力，另一方面可以完成反相还原极性，因为数据选择器输入信号是和。
三、全加器线路图:
四、全加器网表:
fulladder.sp文件:
* SPICE netlist written by S-Edit Win32 2.06
* Written on Jun 12, 2011 at 23:16:01
* Waveform probing commands
.probe中空半自动打胶机
.options probefilename="Module0.dat"
+ probesdbfile="H:\fulladder\fulladder.sdb"
+ probetopmodule="Module0"
.include "H:\fulladder\ml2_125.md"
VPower Vdd Gnd 5
va A Gnd PULSE (0 5 50n 5n 5n 50n 100n)
vb B Gnd BIT ({0011} lt= 50n ht= 50n on=5 off=0 rt=5n ft=5n)
vci Ci Gnd PWL (0ns 0V 200ns 0V 205ns 5V 400ns 5V)
.tran 1n 400n
.print tran v(A) v(B) v(Ci) v(S) v(Co)
* Main circuit: Module0
M1 N13 A Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M2 N14 N12 Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M3 N10 N13 B Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M4 N12 A B Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M5 N6 Ci Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M6 N2 N1 Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M7 Co N5 Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M8 N12 B A Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M9 N10 B N13 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
伯努利方程实验M10 N6 N10 N1 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M11 Ci N12 N1 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M12 N13 N12 N5 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M13 N6 N10 N5 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
M14 S N2 Gnd Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
按摩脚盆M15 N13 A Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M16 N14 N12 Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M17 N10 A B Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M18 N12 N13 B Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M19 N6 Ci Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M20 N2 N1 Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
喷雾面膜M21 Co N5 Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M22 N12 B N13 Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M23 N10 B A Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M24 N6 N14 N1 Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M25 Ci N10 N1 Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M26 N13 N12 N5 Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M27 N6 N12 N5 Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
M28 S N2 Vdd Vdd PMOS L=2u W=9u AD=66p PD=24u AS=66p PS=24u
* End of main circuit: Module0
fulladder.spc文件:
* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;
* TDB File: H:\fulladder\fulladder, Cell: Cell0
* Extract Definition File: C:\Program Files\Tanner EDA\L-Edit\
* Extract Date and Time: 06/12/2011 - 22:58
.include "H:\fulladder\ml2_125.md"
VPower VDD GND 5
va A GND PULSE (0 5 50n 5n 5n 50n 100n)
vb B GND BIT ({0011} lt= 50n ht= 50n on=5 off=0 rt=5n ft=5n)
vci Ci GND PWL (0ns 0V 200ns 0V 205ns 5V 400ns 5V)
.tran 1n 400n
.print tran v(A) v(B) v(Ci) v(S) v(Co)
* WARNING: Layers with Unassigned AREA Capacitance.
* <Poly Resistor>
* <Poly2 Resistor>
* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* WARNING: Layers with Unassigned FRINGE Capacitance.
* <Pad Comment>
* <Poly Resistor>
* <Poly2 Resistor>
磨头* <N Diff Resistor>
* <P Diff Resistor>
* <N Well Resistor>
* <P Base Resistor>
* <Poly1-Poly2 Capacitor>
* WARNING: Layers with Zero Resistance.
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