LTC2262-12中文资料

T YPICAL APPLICATION
F EATURES
A PPLICATIONS
D ESCRIPTION Ultralow Power 1.8V ADC
n
Communications n  Cellular Base Stations n  Software Defi ned Radios n  Portable Medical Imaging
n  Multi-Channel Data Acquisition n  Nondestructive Testing
L , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
n
70.5dB SNR n  88dB SFDR
n  Low Power: 146mW n  Single 1.8V Supply
n  CMOS, DDR CMOS or DDR LVDS Outputs n  Selectable Input Ranges: 1V P-P  to 2V P-P  n  800MHz Full-Power Bandwidth S/H n  Optional Data Output Randomizer n  Optional Clock Duty Cycle Stabilizer n  Shutdown and Nap Modes n  Serial SPI Port for Confi guration
n  Pin Compatible 14-Bit and 12-Bit Versions n  40-Pin (6mm × 6mm) QFN Package
The LTC ®2262-12 is a sampling 12-bit A/D converter
designed for digitizing high frequency, wide dynamic range signals. The LTC2262-12 is perfect for demanding commu-nications applications with AC performance that includes 70.5dB SNR and 88dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17ps RMS  allows undersampling of IF frequencies with excellent noise performance.
DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSB RMS .
The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.
The ENC + and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al-lows high performance at full speed for a wide range of clock duty cycles.
2-Tone FFT , f IN  = 68MHz and 69MHz
150MHz CLOCK
ANALOG INPUT
DD
FREQUENCY (MHz)
0–100–110–120
–70–60–80
–90A M P L I T U D E  (d B F S )
–50–30–40–20–1001020
30405070
60226212 TA01b
LTC2262-12
A BSOLUTE MAXIMUM RATINGS Supply Voltages (V DD , OV DD ) .......................–0.3V to 2V Analog Input Voltage (A IN +, A IN –,
PAR/SER , SENSE) (Note 3) ...........–0.3V to (V DD  + 0.2V)Digital Input Voltage (ENC +, ENC –, CS ,
SDI, SCK) (Note 4) ....................................–0.3V to 3.9V SDO (Note 4) ............................................–0.3V to 3.9V
(Notes 1, 2)
39403837363534333231
1120
12131415FULL-RATE CMOS OUTPUT MODE
TOP VIEW
41
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16171819222324252627282998
765432A IN +A IN –GND REFH REFH REFL REFL PAR/SER V DD V DD D7D6CLKOUT +CLKOUT –OV DD OGND D5D4D3D2
V D D
S E N S E
V R E F
V C M
O F
D N C
D 11
D 10
D 9
D 8
E N C +
E N C –
C S
S C K
S D I
S D O
D N C
D N C
D 0
D 1
213010
1T JMAX  = 150°C, θJA  = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
39403837363534333231
1120
12131415DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
41
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16171819222324252627282998
765432A IN +A IN –GND REFH REFH REFL REFL PAR/SER V DD V DD D6_7DNC CLKOUT +CLKOUT –
OV DD OGND D4_5DNC D2_3DNC
V D D
S E N S E
V R E F
V C M
O F
D N C
D 10_11
D N C
D 8_9D N C
E N C +
E N C –
C S
S C K
人脸识别巡更系统S D I
S D O
D N C
D N C
D N C
D 0_1
213010
1T JMAX  = 150°C, θJA  = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
39403837363534333231
1120
12131415DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
41
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
16171819222324252627282998
765432A IN +A IN –GND REFH REFH REFL REFL PAR/SER V DD V DD D6_7+D6_7–CLKOUT +CLKOUT –
OV DD OGND D4_5+D4_5–D2_3+D2_3–
V D D
S E N S E
V R E F
V C M
O F +
O F –
D 10_11+
D 10_11–
D 8_9+D 8_9–
E N C +
E N C –
C S
S C K
S D I
S D O
D N C
D N C亚克力水晶制作
D 0_1–
D 0_1+
213010
1T JMAX  = 150°C, θJA  = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
P IN CONFIGURATIONS Digital Output Voltage ................–0.3V to (OV DD  + 0.3V)Operating Temperature Range:
L TC2262C ................................................0°C to 70°C  –40°C to 85°C Storage Temperature Range ...................–65°C to 150°C
LTC2262-12
CONVERTER CHARACTERISTICS  The l  denotes the specifi cations which apply over the full operating门槛记
temperature range, otherwise specifi cations are at T A  = 25°C. (Note 5)
五方通话系统
PARAMETER
CONDITIONS
MIN TYP MAX UNITS Resolution (No Missing Codes)l
12Bits Integral Linearity Error Differential Analog Input (Note 6)l –1±0.31LSB Differential Linearity Error Differential Analog Input l –0.4±0.10.4LSB Offset Error (Note 7)l –9±1.59mV Gain Error Internal Reference External Reference l
–1.5
±1.5
±0.4  1.5
%FS %FS Offset Drift ±20μV/°C Full-Scale Drift Internal Reference External Reference ±30±10ppm/°C ppm/°C T ransition Noise
External Reference
0.3
LSB RMS
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION
TEMPERATURE RANGE L TC2262CUJ-12#PBF L TC2262CUJ-12#TRPBF L TC2262UJ-1240-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C L TC2262IUJ-12#PBF
L TC2262IUJ-12#TRPBF
L TC2262UJ-12
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container .Consult L TC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: www.linear /leadfree/ For more information on tape and reel specifi cations, go to: www.linear /tapeandreel/
ANALOG INPUT  The l  denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at T A  = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN + – A IN –)
1.7V < V DD  < 1.9V
l    1 to 2V P-P V IN(CM)Analog Input Common Mode (A IN + + A IN –)/2Differential Analog Input (Note 8)l V CM  – 100mV
V CM V CM  + 100mV
V V SENSE External Voltage Reference Applied to SENSE External Reference Mode
l
0.625  1.250  1.300V I INCM Analog Input Common Mode Current Per Pin, 150Msps
185
μA I IN1Analog Input Leakage Current 0 < A IN +, A IN – < V DD , No Encode l –11μA I IN2PAR/SER
  Input Leakage Current 0 < PAR/SER  < V DD l –33μA I IN3SENSE Input Leakage Current
0.625V < SENSE < 1.3V
l –6
6
μA t AP Sample-and-Hold Acquisition Delay Time 0ns t JITTER Sample-and-Hold Acquisition Delay Jitter 0.17ps RMS
CMRR Analog Input Common Mode Rejection Ratio 80dB BW-3B
Full-Power Bandwidth
Figure 6 Test Circuit
800
MHz
LTC2262-12
DYNAMIC ACCURACY
The l  denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A  = 25°C. A IN  = –1dBFS. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR
Signal-to-Noise Ratio
5MHz Input
30MHz Input 70MHz Input 140MHz Input l
70.570.470.370.1dB dB dB dB SFDR
Spurious Free Dynamic Range 2nd or 3rd Harmonic
5MHz Input 30MHz Input 70MHz Input 140MHz Input l
88888281dB dB dB dB Spurious Free Dynamic Range 4th Harmonic or Higher
5MHz Input 30MHz Input 70MHz Input 140MHz Input l
90909090dB dB dB dB S/(N+D)Signal-to-Noise Plus Distortion Ratio
5MHz Input 30MHz Input 70MHz Input 140MHz Input
l
70.470.37069.8
dB dB dB dB
INTERNAL REFERENCE CHARACTERISTICS  The l  denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at T A  = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
V CM  Output Voltage I OUT  = 0
0.5 • V DD  – 25mV
0.5 • V DD 0.5 • V DD  + 25mV
V V CM  Output Temperature Drift ±25ppm/°C
V CM  Output Resistance –600μA < I OUT  < 1mA 4ΩV REF  Output Voltage I OUT  = 0
1.225  1.250  1.275V V REF  Output Temperature Drift ±25ppm/°C
V REF  Output Resistance –400μA < I OUT  < 1mA 7ΩV REF  Line Regulation
1.7V < V DD  < 1.9V
0.6
mV/V
SYMBOL PARAMETER CONDITIONS
MIN TYP MAX UNITS
ENCODE INPUTS (ENC +, ENC – )
Differential Encode Mode (ENC – Not Tied to GND)V ID Differential Input Voltage (Note 8)
l 0.2
V V ICM Common Mode Input Voltage Internally Set
Externally Set (Note 8)l    1.1  1.2
1.6V V V IN Input Voltage Range ENC +, ENC – to GND l
0.2
3.6
V R IN Input Resistance (See Figure 10)10kΩC IN Input Capacitance (Note 8)  3.5
pF Single-Ended Encode Mode (ENC – Tied to GND)
V IH High Level Input Voltage V DD  = 1.8V l    1.2
V V IL Low Level Input Voltage V DD  = 1.8V l 0.6
V V IN Input Voltage Range ENC + to GND l 0
3.6V R IN Input Resistance (See Figure 11)30kΩC IN
Input Capacitance
(Note 8)
3.5
pF
DIGITAL INPUTS AND OUTPUTS  The l  denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T A  = 25°C. (Note 5)
LTC2262-12
DIGITAL INPUTS AND OUTPUTS
The
l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK)
V IH High Level Input Voltage V DD = 1.8V l  1.3V V IL Low Level Input Voltage V DD = 1.8V l0.6V I IN Input Current V IN = 0V to 3.6V l–1010μA C IN Input Capacitance(Note 8)3pF SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R OL Logic Low Output Resistance to GND V DD = 1.8V, SDO = 0V200ΩI OH Logic High Output Leakage Current SDO = 0V to 3.6V l–1010μA C OUT Output Capacitance(Note 8)4pF DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV DD = 1.8V
V OH High Level Output Voltage I O = –500μA l  1.750  1.790V V OL Low Level Output Voltage I O = 500μA l0.0100.050V OV DD = 1.5V
V OH High Level Output Voltage I O = –500μA  1.488V V OL Low Level Output Voltage I O = 500μA0.010V OV DD = 1.2V
V OH High Level Output Voltage I O = –500μA  1.185V V OL Low Level Output Voltage I O = 500μA0.010V DIGITAL DATA OUTPUTS (LVDS MODE)
V OD Differential Output Voltage100Ω Differential Load, 3.5mA Mode
铸铁锅炉
100Ω Differential Load, 1.75mA Mode l247350
175
454mV
mV
V OS Common Mode Output Voltage100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode l  1.125  1.250
1.250
1.375V
V
R TERM On-Chip Termination Resistance Termination Enabled, OV DD = 1.8V100Ω
POWER REQUIREMENTS
The
l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
V DD Analog Supply Voltage(Note 10)l  1.7  1.8  1.9V OV DD Output Supply Voltage(Note 10)l  1.1  1.9V
I VDD Analog Supply Current DC Input
Sine Wave Input l80.9
82.7
mA
mA
I OVDD Digital Supply Current Sine Wave Input, OV DD=1.2V  5.1mA
P DISS Power Dissipation DC Input
Sine Wave Input, OV DD=1.2V l146
155
mW
mW

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