December 12, 2007 LP3907
Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
General Description
The LP3907 is a multi-function, programmable Power Man-agement Unit, optimized for low power FPGAs, microproces-sors and DSPs. This device integrates two highly efficient 1A/ 600mA step-down DC/DC converters with dynamic voltage management (D VM), two 300mA linear regulators and a 400kHz I2C compatible interface to allow a host controller ac-cess to the internal control registers of the LP3907. The LP3907 additionally features programmable power-on se-quencing. Package options include a tiny 4 x 4 x 0.8mm LLP 24–pin package and an even smaller 2.5 x 2.5mm micro SMD 25-bump package.
Key Specifications
Step-Down DC/DC Converter (Buck)
■1A/600mA output current
■Programmable V OUT from:
—Buck1 : 0.8V–2.0V @ 1A
—Buck2 : 1.0V–3.5V @ 600mA
■Up to 96% efficiency
■ 2.1MHz PWM switching frequency
■PWM - PFM automatic mode change under low loads
■±3% output voltage accuracy
■Automatic soft start
Linear Regulators (LDO)
■Programmable V OUT of 1.0V–3.5V
■±3% output voltage accuracy
■300mA output current
■30mV (typ) dropout Features
■Compatible with advanced applications processors and FPGAs
■ 2 LDOs for powering Internal processor functions and I/Os ■High speed serial interface for independent control of device functions and settings
■Precision internal reference
■Thermal overload protection
■Current overload protection
■24-lead 4 × 4 × 0.8mm LLP or 25–bump 2.5 x 2.5mm micro SMD package
■Software Programmable Regulators
■External Power-on-reset function for Buck1 and Buck2
(i.e., Power Good with delay function)
■Undervoltage lock out detector to monitor input supply voltage
Applications
■FPGA, DSP core power
■Applications processors
■Peripheral I/O power
© 2007 National Semiconductor LP3907 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
Typical Application Circuit
30017801
FIGURE 1. Application Circuit
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LP3907
30017802
FIGURE 2. Application Circuit
Connection Diagrams and Package Mark Information
30017803
24-Lead LLP Package (top view
Note:The physical placement of the package marking will vary from part to part.
(*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code. See /quality/marking_conventions.html for more information on marking information.
(**) Package received will have XXXX replaced with the specific part version ordered.
25-Bump Thin Micro SMD Package, Large Bump National Package Number TLA25AAA
30017890
Top View
30017889
Bottom View
30017888
Package Mark - Top View
4
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Ordering Information
Voltage Option Order Number Package Type NSC Package
Drawing
Package Marking Supplied As
Voltage “PXPP”LP3907SQ-PXPP24-lead LLP SQA024AE07-PXPP1000 tape & reel Voltage “PXPP”LP3907SQX-PXPP24-lead LLP SQA024AE07–PXPP4500 tape & reel Voltage “JXQX”LP3907SQ-JXQX24-lead LLP SQA024AE07–JXQX1000 tape & reel Voltage “JXQX”LP3907SQX-JXQX24-lead LLP SQA024AE07–JXQX4500 tape & reel Voltage “JXQX”LP3907SQ-JXQX**24-lead LLP SQA024AE07PJXQX1000 tape & reel Voltage “JXQX”LP3907SQX-JXQX**24-lead LLP SQA024AE07PJXQX4500 tape & reel Voltage “JIXI”LP390
7SQ-JIXI24-lead LLP SQA024AE07–JIXI1000 tape & reel Voltage “JIXI”LP3907SQX-JIXI24-lead LLP SQA024AE07–JIXI4500 tape & reel Voltage “JSXS”LP3907TL-JSXS25–bump micro
SMD
TLA25AAA V012250 tape & reel
Voltage “JSXS”LP3907TLX-JSXS25–bump micro
SMD
TLA25AAA V0123000 tape & reel ** For Forced PWM Buck Regulators use spec # S7001874 when ordering.
Default Voltage Options
Regulator Version “PXPP” Default
Voltages (V)Version “JXQX” Default
Voltages (V)
Version “JSXS” Default
Voltages (V)
Version “JIXI” Default
Voltages (V)
SW1 1.5 1.2 1.2 1.2
SW2 3.3 3.3 2.8 3.3
LDO1 2.5 2.6 3.3 1.8
LDO2 2.5 3.3 2.8 3.3
Package Type Default I2C Address
24–lead LLP60
25–bump micro SMD61
LP3907
Pin Descriptions
LLP Pin No.
micro SMD pin no.Name I/O Type Description
1B4, B5VINLDO12I PWR Analog Power for Internal Functions (VREF, BIAS, I2C,Logic)
2C4EN_T I D Enable for preset power on sequence. (see page 20)3
C3
nPOR
O
D
nPOR Power on reset pin for both Buck1 and Buck 2.Open drain logic output 100K pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See nPOR section for more info.4C5GND_SW1G G Buck1 NMOS Power Ground 5D5SW1O PWR Buck1 switcher output pin
6E5VIN1I PWR Power in from either DC source or Battery to Buck17D4ENSW1I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
8E4FB1I A Buck1 input feedback terminal 9D3GND_C G G Non switching core ground pin 10E3AVDD I PWR Analog Power for Buck converters 11E2FB2I A Buck2 input feedback terminal
12D2ENSW2I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
13E1VIN2I PWR Power in from either DC source or Battery to Buck214D1SW2O PWR Buck2 switcher output pin 15C1GND_SW2G G Buck2 NMOS Power ground 16C2SDA I/O D I 2C Data (bidirectional)17B2SCL I D I 2C Clock 18B1GND_L G G LDO ground
19A1VINLDO1I PWR Power in from either DC source or battery to input terminal to LDO120A2LDO1O PWR LDO1 Output
21B3ENLDO1I D LDO1 enable pin, a logic HIGH enables the LDO122A3ENLDO2I D LDO2 enable pin, a logic HIGH enables the LDO223A4LDO2O PWR LDO2 Output
24
A5
VINLDO2
I
PWR
Power in from either DC source or battery to input terminal to LDO2
A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin.
Power Block Operation
Note Power Block Input Enabled Disabled
VINLDO12VIN+VIN+Always Powered AVDD VIN+VIN+Always Powered VIN1VIN+VIN+ or 0V VIN2VIN+
VIN+ or 0V
LDO 1≤ VIN+≤ VIN+If Enabled, Min Vin is 1.74V LDO 2
≤ VIN+≤ VIN+
If Enabled, Min Vin is 1.74V
VIN+ is the largest potential voltage on the device.
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