MC74LVX4245
Dual Supply Octal
Translating Transceiver
with 3−State Outputs
The 74LVX4245 is a 24−pin dual−supply, octal translating transceiver that is designed to interface between a 5.0 V bus and a 3.0 V bus in a mixed 3.0 V / 5.0 V supply environment such as laptop computers using a 3.3 V CPU and 5.0 V LCD display. The A port interfaces with the 5V bus; the B port interfaces with the 3.0 V bus.The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active−High) enables data from the A port to the B port. Receive (active−Low) enables data fr不锈钢钝化 om the B port to the A port.The Output Enable (OE) input, when High, disables both A and B ports by placing them in 3−State.
Features
•Bi−directional Interface Between 5.0 V and 3.0 V Buses •Control Inputs Compatible with TTL Level
•5.0 V Data Flow at A Port and 3.0 V Data Flow at B Port
•Outputs Source/Sink 24 mA at 5.0 V Bus and 12 mA at 3.0 V Bus •Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance
•Available in SOIC and TSSOP Packages冷库蒸发器 •Functionally Compatible with the 74 Series 245•
Pb−Free Packages are Available*
Figure 1. 24−Lead Pinout
(Top View)
23
24
22
21
20
19
18
2134
通用积分
567V CCB 17
816
915
10V CCB OE B0B1B2B3B4B5B6V CCA T/R
A0
A1
A2
A3
A4
A5
A6
A7
14
1113
12
十二水磷酸氢二钠B7GND GND GND
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
onsemi
MARKING DIAGRAMS
SOIC−24
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
24
LVXC4245AWLYYWW A =Assembly Location WL =Wafer Lot YY =Year
WW =
Work Week
LVX 4245AWLYYWW
124
TSSOP−24DT SUFFIX CASE 948H
B0
OE 22T/R 2A0
B1A1
B2A2
B3A3
B4A4
B5A5
B6A6
2mcB7A7
Figure 2. Logic Diagram
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions are Acceptable; For I CC reasons, Do Not Float Inputs
ABSOLUTE MAXIMUM RATINGS
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
2.Max number of outputs defined as (n). Data inputs are driven 0V to V CC level; one output at GND.
翻板百叶
3.Max number of data inputs (n) switching. (n−1) inputs switching 0V to V CC level. Input under test switching: V CC level to threshold (V IHD),
0V to threshold (V ILD), f = 1MHz.
CAPACITIVE CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
CCA CCB
5.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OS
HL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.
ORDERING INFORMATION
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual−supply device well capable of bidirectional signal voltage translation. This level shifting ability provides an excellent interface between low voltage CPU local bus and a standard 5.0 V I/O bus. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5.0 V I/O levels. The L VX4245 is ideal for mixed voltage applic
ations such as notebook computers using a 3.3 V CPU and 5.0 V peripheral devices.
Applications:
Mixed Mode Dual Supply Interface Solutions
The L VX4245 is designed to solve 3.0 V / 5.0 V interfaces
when CMOS devices cannot tolerate I/O levels above their applied V CC. If an I/O pin of a 3.0 V device is driven by a 5.0 V device, the P−Channel transistor in the 3.0 V device will conduct − causing current flow from the I/O bus to the 3.0 V power supply. The result may be destruction of the 3.0 V device through latchup effects. A current limiting resistor may be used to prevent destruction, but it causes speed degradation and needless power dissipation.
A better solution is provided in the LVX4245. It provides two different output levels that easily handle the dual voltage interface. The A port is a dedicated 5.0 V port; the
B port is a dedicated 3.0 V port.
Since the LVX4245 is a ‘245 transceiver, the user may either use it for bidirectional or unidirectional a
pplications. The center 20 pins are configured to match a ‘245 pinout. This enables the user to easily replace this level shifter with a 3.0 V ‘245 device without additional layout work or re−manufacture of the circuit board (when both buses are 3.0 V).
Figure 3. 3.3V/5V Interface Block Diagram
LVX4245
V CCB
V CCA
LVX4245
V CCB
V CCA
EISA − ISA − MCA
(5V I/O LEVELS)
LOW VOLTAGE CPU LOCAL BUS
Powering Up the LVX4245
When powering up the LVX4245, please note that if the V CCB pin is powered−up well in advance of the V CCA pin, several milliamps of either I CCA or I CCB current will result. If the V CCA pin is powered−up in advance of the V CCB pin then only nanoamps of Icc current will result. In actuality the V CCB can be powered “slightly” before the V CCA without the current penalty, but this “setup time” is dependent on the power−up ramp rate of the V CC pins. With a ramp rate of approximately 50 mV/ns (50V/m s) a 25 ns setup time was observed (V CCB before V CCA). With a 7.0 V/m s rate, the setup time was about 140ns. When all is said and done, the safest powerup strategy is to simply power V CCA before V CCB. One more note: if the V CCB ramp rate is faster than the V CCA ramp rate then power problems might still occur, even if the V CCA powerup began prior to the V CCB powerup.
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