首页 > 专利技术

用一位全加器设计8位串、并行的加法计数器

1.只用一个1位二进制全加器为基本元件和一些辅助的时序电路，设计一个8自动化运维系统位串行二进制全加器电子式电压互感器

半加器（VHDL)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_adder IS

PORT ( a , b : IN STD_LOGIC ;

co, so : OUT STD_LOGIC );

END ENTITY h_adder;

ARCHITECTURE one OF h_adder IS

BEGIN

so<=NOT(a XOR (NOT b)); co <= a AND b ;

END ARCHITECTURE one;

D触发器（VHDL）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DFF1 IS

PORT ( CLK : IN STD_LOGIC;

D : IN STD_LOGIC;

Q : OUT STD_LOGIC);

END;

ARCHITECTURE bhv OF DFF1 IS

SIGNAL Q1 : STD_LOGIC;

BEGIN

PROCESS( CLK,D)

BEGIN

IF CLK='1'

THEN Q1<=D;

END IF;

END PROCESS;

Q<=Q1;

END bhv;

串并移位寄存器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SHFRT1 IS

PORT (CLK,LOAD : IN STD_LOGIC;

DIN : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);

QB : OUT STD_LOGIC );

END SHFRT1;

ARCHITECTURE behav OF SHFRT1 IS

BEGIN

PROCESS( CLK, LOAD)

VARIABLE REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF CLK'EVENT AND CLK = '1' THEN

IF LOAD='1' THEN REG8 :=DIN;

ELSE REG8(6 DOWNTO 0) :=REG8 (7 DOWNTO 1);

END IF;

QB <=REG8(0);

END PROCESS;

END behav;

并串移位寄存器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

贴片led封装ENTITY SHFRT IS

离心离合器

PORT (CLK : IN STD_LOGIC;

DIN : OUT STD_LOGIC_VECTOR( 15 DOWNTO 8);

QB : IN STD_LOGIC );

END SHFRT;

ARCHITECTURE behav OF SHFRT IS

BEGIN

PROCESS( CLK )

VARIABLE REG8 : STD_LOGIC_VECTOR(15 DOWNTO 8);

BEGIN

IF CLK'EVENT AND CLK = '1'

THEN REG8(8) := QB;

REG8(15 DOWNTO 9) :=REG8 (14 DOWNTO 8);

END IF;

口香糖电池

END PROCESS;

END behav;

2.用一位全加器为基本单元设计8位并行的全加器

VHDL木质骨灰盒源程序代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_ADDER IS

PORT (A, B : IN STD_LOGIC;

CO, SO : OUT STD_LOGIC );

END ENTITY H_ADDER;

ARCHITECTURE FH1 OF H_ADDER IS

BEGIN

SO <= NOT (A XOR (NOT B));

CO <= A AND B;

END ARCHITECTURE FH1;

程序2：一位二进制全加器设计顶层描述

功能：程序功能简介

VHDL源程序代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F_ADDER IS

PORT (AIN, BIN, CIN : IN STD_LOGIC;

COUT, SUM : OUT STD_LOGIC );

END ENTITY F_ADDER;

ARCHITECTURE FD1 OF F_ADDER IS

COMPONENT H_ADDER IS

PORT (A, B : IN STD_LOGIC;

CO, SO : OUT STD_LOGIC );

END COMPONENT;

SIGNAL D, E, F : STD_LOGIC;

BEGIN

U1 : H_ADDER PORT MAP(A => AIN, B => BIN, CO => D, SO => E);

U2 : H_ADDER PORT MAP(A => E, B => CIN, CO => F, SO => SUM);

COUT <= D OR F;

END ARCHITECTURE FD1;

程序3：8位并行二进制全加器顶层文件

功能：程序功能简介

VHDL源程序代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F_ADDER8 IS

PORT ( AIN, BIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CIN : IN STD_LOGIC;

SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

COUT : OUT STD_LOGIC );

END F_ADDER8;

ARCHITECTURE ONE OF F_ADDER8 IS

COMPONENT F_ADDER IS

PORT (AIN, BIN, CIN : IN STD_LOGIC;

COUT, SUM : OUT STD_LOGIC );

END COMPONENT;

SIGNAL C1, C2, C3,C4,C5,C6,C7: STD_LOGIC;

BEGIN

U1 : F_ADDER PORT MAP(AIN => AIN(0), BIN => BIN(0), CIN => CIN, SUM => SUM(0), COUT => C1);

U2 : F_ADDER PORT MAP(AIN => AIN(1), BIN => BIN(1), CIN => C1, SUM => SUM(1), COUT => C2);

U3 : F_ADDER PORT MAP(AIN => AIN(2), BIN => BIN(2), CIN => C2, SUM => SUM(2), COUT => C3);

U4 : F_ADDER PORT MAP(AIN => AIN(3), BIN => BIN(3), CIN => C3, SUM => SUM(3), COUT => C4);

U5 : F_ADDER PORT MAP(AIN => AIN(4), BIN => BIN(4), CIN => C4, SUM => SUM(4), COUT => C5);

U6 : F_ADDER PORT MAP(AIN => AIN(5), BIN => BIN(5), CIN => C5, SUM => SUM(5), COUT => C6);

U7 : F_ADDER PORT MAP(AIN => AIN(6), BIN => BIN(6), CIN => C6, SUM => SUM(6), COUT => C7);

U8 : F_ADDER PORT MAP(AIN => AIN(7), BIN => BIN(7), CIN => C7, SUM => SUM(7), COUT => COUT);

END ONE;

本文发布于:2024-09-22 21:31:09，感谢您对本站的认可！

本文链接：https://www.17tex.com/tex/3/244342.html

上一篇：计算机组成原理试题及答案全解

下一篇：第三章运算方法

标签：功能运维电子式骨灰盒基本

留言与评论（共有 0 条评论）