Summary
Many systems use byte-wide peripheral interface (BPI) flash memory for FPGA configuration and system data storage. Often it is not desirable or even possible to update the flash PROM directly after the system is deployed. One approach to address this issue is to use the FPGA to program the PROM to which it is connected. This methodology is called in-system
programming (ISP). An example of ISP is the indirect programming capability supported by iMPACT (a tool featuring batch and GUI operations). In this case, iMPACT uses the JTAG interface port as the communication channel between a host and the FPGA. The iMPACT tool sends the bit file to the FPGA, which in turn programs the PROM attached to it.
However, many embedded systems do not have such JTAG interface connections available. The FPGA is often an endpoint device on the PCI Express® bus. Because no JTAG interface channel is available through the standard PCIe® peripheral, the only way to program a PROM on the endpoint is to program across the PCIe system.
This application note provides an ISP reference design to demonstrate the methodology and considerations of programming in-system BPI PROM for Virtex®-6, Virtex®-7, and Kintex®-7 FPGAs in
a PCIe system.
Overview
Figure 1 shows the high-level block diagram of the ISP reference design. The design comprises three major components: an integrated block for PCI Express core, a buffer, and a programming state machine (PSM).
The ISP reference design targets the ML605, VC707, and the KC705 evaluation boards. The ML605 board has an XC6VLX240T -1FFG1156 FPGA connected to a 256 Mb BPI PROM.
Application Note: Virtex-6, Virtex-7, and Kintex-7 Family
XAPP518 (v1.3) April 23, 2014用电信息
采集 In-System Programming of BPI PROM for Virtex-6, Virtex-7, and Kintex-7 FPGAs Using PCI Express Technology
Author: Simon Tam
音调电路Figure 1:High-Level Block Diagram
Integrated Block for PCI Express
Table 1 summarizes the recommended programming command sequence and definitions of each command.
Figure 9 and Figure 10 illustrate the timing diagrams at the beginning and ending of the buffer program stage.
Table 1: Host Software Command Sequence Sequence
Command Word Definition Notes
1Start_Address 0x5341[aaaa]Specifies the starting block address.2
End_Address
0x45[aaaaaa]
Specifies the PROM word end address. Bits 23 to 0 of the command word define the end address.
3Unlock 0x556E6C6B
Unlocks contiguous blocks between the addresses specified in the Start_Address and End_Address
commands.
4Erase 0x45726173
Erases contiguous blocks between the addresses specified in the Start_Address and End_Address commands.
多功能折叠椅5
Program 0x50726F67
Initiates the program sequence. The
programmer reads data from the buffer and writes to the PROM until the end address is reached.
Reference Design Demonstration
Record 8 updates the upper two bytes of the physical address. This address remains valid for
the rest of the file. Table6 describes the fields in the record.
Records 9 to 11 are regular data records. Record 11 is the last data record and often has a
number of data bytes fewer than 16 bytes. T able7 summarizes the fields in record 11.
Reference Design Demonstration This section guides the user through setting up and running the reference design demonstration. The demonstration allows users to program the BPI PROM on a ML605,
VC707, or KC705 board connected to a host system running Windows XP. Pre-built bit files and host software applications are available in the reference design.
System Requirements
对甲苯磺酸吡啶盐These are required for the demonstration:
•ML605 demonstration platform (XC6VLX240T-FF1156 production device), VC707 evaluation board (XC7VX485T-2FFG1761C), or KC705 evaluation board
(XC7K325T-2FFG900C)
•X86 system with Windows XP Service Pack 3 installed
Use these steps to run the reference design demonstration:
1.Extract the ML605.zip, VC707.zip, or the KC705.zip inside the xapp518.zip file to
the <ref_design_dir> directory.
2.Copy all files in <ref_design_dir>\sw\Jungo\system to
<WindowsXP_install_path>\system32.
This step installs the Jungo WinDriver libraries and driver (rev. 10.2) in Windows XP.
COMDLD32.OCX should be backed up if the file already exists.
3.Set DIP switch on the board as follows to enable BPI flash programming:
•For the ML605 board:
-S2-1 = ON
-S2-2 = ON
Table 6: Record 8 Descriptions
Field Content Description
DataLength02There are two data bytes in the data field.
Address0000The address field is always 0x0000 for an ELA record. RecordType04This is an ELA record.
Data0021The upper two address bytes are 0x0000.
CheckSum D9Checksum is 0xD9.
垃圾分类器Table 7: Record 11 Descriptions Field Content Description
DataLength0C There are 12 data bytes in the data field.
Address BB70
The absolute address is the concatenation of this address field
and the current ELA defined in record 1. Therefore, it is
0x0021BB70.
RecordType00This is a regular data record.
Data<data>There are 12 bytes of data.
CheckSum E8Checksum is 0xBD.
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