PRELIMINARY DATA SHEET
■AC101L
AC101L-DS01-RDC
16215 Alton Parkway •P .O. Box 57013•Irvine, CA 92619-7013•Phone: 949-450-8700•Fax: 949-450-871002/20/02Ultra Low Power 10/100 Ethernet Transceiver with Auto_MDIX Figure 1:AC101L Functional Block Diagram D E S C R I P T I O N
F E A T U R E S The AC101L is a single channel, low power,
10/100BASE-TX/FX Transceiver. The AC101L has an
integrated voltage regulator to allow operation from a
single 3.3V or 2.5V supply source. The device contains a
full-duplex 10BASE-T/100BASE-TX/100BASE-FX Fast
Ethernet transceiver, which performs all of the physical
layer interface functions.
熔断器盒
The AC101L is a highly integrated solution combining a
encoder/decoder, link monitor, auto-negotiation
selection, parallel detection, adaptive equalization, clock/
静压主轴data recovery, base line wander correction, multi mode transmitter, scrambler/descrambler, Far End Fault (FEF),
and auto MDI/MDIX circuitry. It is fully compliant with the
IEEE802.3 and 802.3u standards.• 3.3V tolerant and 2.5V capable •Integrated voltage regulator to allow operation from a single 3.3V or 2.5V supply source •10/100 TX/FX •Full-Duplex or Half-Duplex •FEFI on 100FX •48-pin TQFP •Industrial Temp (-40°C to +85°C) •.25µm CMOS •Fully compliant with IEEE 802.3 / 802.3u •MII/RMII Interface •Baseline Wander Compensation •Multi-Function LED outputs •Cable length indicator •HP auto-MDI/MDIX •
Eight programmable interrupts •Diagnostic registers
R EVISION H ISTORY
Revision #Date Change Description
AC101L-DS00-R01/02/02Initial release.
AC101L-DS01-R02/20/02Second release.
Updated figure 12 and figure 13.
Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, CA 92619-7013
© Copyright 2002 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom® and the pulse logo® are registered trademarks of Broadcom Corporation and/or its subs
idiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.
Preliminary Data Sheet■AC101L 02/20/02
T ABLE OF C ONTENTS
Section 1: Functional Description (1)
Encoder/Decoder (1)
Link Monitor (1)
Carrier Sense (CRS)/RXDV (2)智能控制
方法 Collision Detection (2)
Auto-Negotiation (2)
Parallel Detection (3)
Analog Adaptive Equalizer (3)
Clock Recovery (3)
Baseline Wander Correction (3)
Multi Mode Transmitter (4)
Stream Cipher Scrambler/Descrambler (4)
FEF (Far End Fault) (4)
Transmit Driver (5)
HP-Auto MDI/MDIX (5)
MAC Interface (5)
MII (5)
RMII (5)
SMI (6)
Physical Layer Interfaces (6)
Section 2: Pin Descriptions (7)
Section 3: Pin Diagram (10)
Section 4: Operational Description (11)
Reset (11)
Power Source (11)
Power Saving Mode (11)
Clock Source (11)
Isolate Mode (12)
Loop Back Mode (12)
Interrupt Mode (12)
LED Operation (12)
Broadcom Corporation
Document AC101L-DS01-RDC Page iii
■AC101L Preliminary Data Sheet
02/20/02
LED Interface (12)
LED Configuration Section (12)
LED [3:0] Event Table (13)
Section 5: Register Description (14)
TP PHY Register Summary (14)
Register 0: Control Register (15)
Register 1: Status Register (16)
Register 2: PHY Identifier 1 Register (17)
Register 3: PHY Identifier 2 Register (17)
锦纶6切片Register 4: Auto-Negotiation Advertisement Register (18) Register 5: Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message (19)
Register 6: Auto-Negotiation Expansion Register (19)
Register 7: Auto-Negotiation Next Page Transmit Register (20)
Register 16: BT and Interrupt Level Control Register (20)
Register 17: Interrupt Control/Status Register (21)
Register 18: Diagnostic Register (21)
Register 19: Power/Loopback Register (22)
Register 20: Cable Measurement Capability Register (22)
Register 21: Receive Error Counter (22)
Register 22: Power Management Register (23)
活性氟化钾Register 23: Operation Mode Register (23)
Register 24: CRC for Recent Received Packet (24)
Common Registers (24)
Common Register 0 (Map to Reg. 28) Mode Control Register (24)
Common Register 1: (Map to Reg. 29, Page 0 a28.[15:12]=0000) Test Mode Register (25)
Common Register 4: (Map to Reg. 29, Page 1 a28.[15:12]=0001) LED Blink Rate (25)
Common Register 5: (Map to Reg. 30, Page 1 a.28.[15:12]=0001) LED0 Setting1 Register (25)
Common Register 6: (Map to Reg. 31, Page 1 a.28.[15:12]=0001) LED0 Setting2 Register (26)
Common Register 7: (Map to Reg. 29, Page 2 a.28.[15:12]=0010) LED1 Setting1 Register (26)
Common Register 8: (Map to Reg. 30, Page 2 a.28.[15:12]=0010) LED1 Setting2 Register (26)
Common Register 9: (Map to Reg. 31, Page 2 a.28.[15:12]=0010) LED2 Setting1 Register (26)
Common Register 10: (Map to Reg. 29, Page 3 a.28.[15:12]=0011) LED2 Setting2 Register (27)
Common Register 11: (Map to Reg. 30, Page 3 a.28[.15:12]=0011) LED3 Setting1 Register (27)
Common Register 12: (Map to Reg. 31, Page 3 a.28.[15:12]=0011) LED3 Setting2 Register (27)
Broadcom Corporation
Page iv Document AC101L-DS01-RDC
Preliminary Data Sheet■AC101L 02/20/02
Section 6: 4B/5B Code-Group (28)
Section 7: SMI Read/Write Sequence (29)
Section 8: Timing and AC Characteristics (30)
Clock Timing (30)
Reset Timing (30)
Management Data Interface Timing (31)
100BASE-TX/FX MII Transmit System Timing (32)
100BASE-TX/FX MII Receive System Timing (33)
10BASE-T MII Transmit System Timing (34)
10BASE-T MII Receive System Timing (35)
RMII Transmit Timing (36)
RMII Receive Timing (37)
Copper Application Termination (38)
Section 9: Electrical Characteristics (39)
Absolute Maximum Ratings (39)
Recommended Operating Conditions (39)
Electrical Characteristics (40)
Section 10: Fiber Application Termination (41)
Section 11: Power and Ground Filtering (42)零时刻
Section 12: Mechanical Information (43)
Section 13: Thermal Specifications (44)
Section 14: Ordering Information (45)
Broadcom Corporation
Document AC101L-DS01-RDC Page v
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