【EP3528283A1】逻辑使用本公开的标准商品可编程序逻辑IC芯片背景...

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E P 3 528 283A 1
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EP 3 528 283A1
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EUROPEAN PATENT APPLICATION
(43)Date of publication:
21.08.2019Bulletin 2019/34
(21)Application number: 19157321.1(22)Date of filing: 14.02.2019(51)Int Cl.:
H01L 23/538(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR Designated Extension States: BA ME
Designated Validation States: KH MA MD TN
(30)Priority:14.02.2018US 201862630369 P
24.05.2018US 201862675785 P 11.09.2018US 201862729527 P 04.10.2018US 201862741513 P 02.11.2018US 201862755415 P 18.11.2018US 201862768978 P 13.02.2019
US 201916275272
(71)Applicant: iCometrue Company Ltd.
Hsinchu County (TW)
(72)Inventors:
•Lin, Mou-Shiung Hsinchu city (TW)•Lee, Jin-Yuan Hsinchu city (TW)
(74)Representative: Lang, Christian
LangPatent Anwaltskanzlei Ingolstädter Straße 580807 München (DE)
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LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS BACKGROUND OF THE DISCLOSURE
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A three-dimensional programmable interconnection system based on a multi-chip package includes: a program-mable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.
EP3 528 283A1
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