1.实验目的
(1) 学习Quartus Ⅱ/ISE Suite/ispLEVER软件的基本使用方法。
(2) 学习GW48-CK或其他EDA实验开发系统的基本使用方法。 (3) 了解VHDL程序的基本结构。
2.实验内容
设计并调试好一个由两个4位二进制加法器级联而成的8位二进制并行加法器,并用GW48-CK或其他EDA实验开发系统(事先应选定拟采用的实验芯片的型号)进行硬件验证。 3.实验要求
(1)画出系统的原理图,说明系统中各主要组成部分的功能。
(2)编写各个VHDL源程序。
(3)根据系统的功能,选好测试用例,画出测试输入信号波形或编号测试程序。
(4)根据选用的EDA实验开发装置编好用于硬件验证的管脚锁定表格或文件。
(5)记录系统仿真、逻辑综合及硬件验证结果。
(6)记录实验过程中出现的问题及解决办法。
4.实验条件
(1)开发条件:Quartus Ⅱ 8.0。
(2)实验设备:GW48-CK实验开发系统。
数显时间继电器
(3)拟用芯片:EPM7128S-PL84。
5.实验设计
溶洞处理1)系统原理图
为了简化设计并便于显示,本加法器电路ADDER8B的设计分为两个层次,其中底层电路包括两个二进制加法器模块ADDER4B,再由这两个模块按照图2.1所示的原理图构成顶层电路ADDER8B。 图2.1 ADDER4B电路原理图
图 2.1 ADDER8B电路原理图
2)VHDL程序
加法器ADDER8B的底层和顶层电路均采用VHDL文本输入,有关VHDL程序如下。
ADDER4B的VHDL源程序:
--ADDER4B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS
PORT(C4:IN STD_LOGIC;
A4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC);
END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
沙发工艺 SIGNAL S5:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL A5,B5:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
A5<='0'&A4;
B5<='0'&B4;
S5<=A5+B5+C4;
S4<=S5(3 DOWNTO 0);
CO4<=S5(4);
END ARCHITECTURE ART;
ADDER8B的VHDL源程序:
--ADDER8B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS
PORT(C8: IN STD_LOGIC;
A8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B8: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S8: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CO8: OUT STD_LOGIC );
END ENTITY ADDER8B;
ARCHITECTURE ART OF ADDER8B IS
COMPONENT ADDER4B IS
PORT(C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4: OUT STD_LOGIC );
END COMPONENT ADDER4B;
SIGNAL SC: STD_LOGIC;
BEGIN
U1:ADDER4B PORT MAP(C4=>C8,A4=>A8(3 DOWNTO 0),B4=>B8(3 DOWNTO 0),S4=>S8(3 DOWNTO 0),CO4=>SC);
U2:ADDER4B PORT MAP(C4=>SC,A4=>A8(7 DOWNTO 4),B4=>B8(7 DOWNTO 4),S4=>S8(7 DOWNTO 4),CO4=>CO8);
END ARCHITECTURE ART;
CTRLS的VHDL程序
--CTRLS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTRLS IS
PORT(CLK: IN STD_LOGIC;
SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY CTRLS;
ARCHITECTURE ART OF CTRLS IS
SIGNAL CNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT="111" THEN
CNT<="000";
ELSE
CNT<=CNT+'1';
END IF;
END IF;
END PROCESS;
SEL<=CNT;
END ARCHITECTURE ART;
DISPLAY的VHDL程序
--DISPLAY.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY IS
PORT( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-- DATAIN: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DATAIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--LEDW: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DISPLAY;
ARCHITECTURE ART OF DISPLAY IS
SIGNAL DATA: STD_LOGIC_VECTOR(3 DOWNTO 0);
-- SIGNAL DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
P1:PROCESS(SEL) IS
BEGIN
CASE SEL IS
WHEN"000"=>COM<="11111110";
WHEN"001"=>COM<="11111101";
WHEN"010"=>COM<="11111011";
WHEN"011"=>COM<="11110111";
WHEN"100"=>COM<="11101111";
WHEN"101"=>COM<="11011111";
WHEN"110"=>COM<="10111111";
WHEN"111"=>COM<="01111111";
WHEN OTHERS=>COM<="11111111";
END CASE;
END PROCESS P1;
--LEDW<=SEL;
P2:PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN"000"=>DATA<=DATAIN(3 DOWNTO 0);
WHEN"001"=>DATA<=DATAIN(7 DOWNTO 4);
-- WHEN"010"=>DATA<=DATAIN(11 DOWNTO 8);
-- WHEN"011"=>DATA<=DATAIN(15 DOWNTO 12);
WHEN OTHERS=>DATA<="0000";
END CASE;
CASE DATA IS
一个度导航
WHEN"0000"=>SEG<="00111111";
WHEN"0001"=>SEG<="00000110";电容分压
WHEN"0010"=>SEG<="01011011";
WHEN"0011"=>SEG<="01001111";
WHEN"0100"=>SEG<="01100110";
WHEN"0101"=>SEG<="01101101";
WHEN"0110"=>SEG<="01111101";
WHEN"0111"=>SEG<="00000111";
WHEN"1000"=>SEG<="01111111";
WHEN"1001"=>SEG<="01101111";
WHEN OTHERS=>SEG<="00000000";
END CASE;
加法器电路
END PROCESS P2;
END ARCHITECTURE ART;
ADDER8B动态扫描的VHDL程序
--ADDER8B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;