Constraints Practical Design for Xilinx!!
该文的版权归Xilinx公司所有！由www.edacn收集整理。Make EDA serve you! When to use Timing Constraints? Constraints add to run time, so don’t use them unless you need to
Faster designs need constraining
—it depends on the speed grade of the device selected, but in general, any design with a clock speed of 50MHz or less and a reasonable number of logic levels (7 or less),doesn’t need timing constraints
—
designs over 50MHz should use timing constraints
Designs with multiple clock should have timing constraints —if you have a signal clock and are under the 50MHz limit above, you will not need timing constraints -you can always add them later if you need to载荷谱
If you have multi-cycle clock paths, you need constraints
—these are paths where you know you have two or more clock cycles for logic to steady-state after an input change
Rule of Thumb:run non-timing driven PAR without constraints, unless you are not reaching your timing goals.
—add constraints sparingly, DO NOT over constrain your design -it won’t help, and increases can increase your run time dramatically!!
Why use Design Constraints?
Constraints allow you to lock your pins after the board pin out is fixed —Xilinx M1.5i software has aut
omatic pin locking, and uses the constraints file to pass these pin locks to future runs of the design
Constraints allow you to give your exact timing requirement to the place and route or fitting software
—for many designs, the constraints are not needed for place and route to meet timing -but are an excellent way to get a detailed static timing report whether or not your design meets your goals
—for more challenging designs, the constraints tell the software where the critical paths are -and where to focus their efforts
To know quickly if your design met your goals
—Xilinx has the best timing analysis tools in the FPGA industry
充电器外壳—applying some simple constraints will allow you to get a quick GO/NO-GO after place and route. The software will tell you all the constraints were met,and you can quickly move on to board debug, without ever looking at a report —if your constraints were not met,Xilinx gives you the level of detail needed to quickly understand why -and where your design needs more work.
建模仿真
What Needs Constraining? Internal clock speed for one or more clocks
I/O speed
Logic using multi-cycle clocks
Pin to pin timing
Pin locations and logic locations
OUT1 X
Y Z<0:9>
2 Levels of Logic I/O Speed
Pin 2 Pin Speed
I/O Speed
Logic
Locations
1 Level of Logic
Q
D
CLK Clk & CE Speed
Pin
Locations
OUT2Pin夹网布
Locations
Types of Constraints Supported Timing Constraints
—
specify delay along logic paths
—allows both “quick and dirty”and “highly detailed”timing control Location Constraints
—specify location of components on FPGA
—specify mapping constraints I N S T M Y _F
M A
P B
L K
N M
B C
I N
S T
F L
O P
1B
L K
N M
=A
B C
I N
S T
F L
O P
2B
L K
N M
=A
B C
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