Preliminary
Brief Data sheet
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
PC1089K
Rev 0.1
Last update : 30. Aug. 2010
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,
Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398
Copyright ⓒ2010, Pixelplus Co.,Ltd
ALL RIGHTS RESERVED
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
▶Revision History
Version Date [D/M/Y]Notes Writer
0.021/07/2010(Preliminary)DS Min
0.130/08/2010Modified PIN description HS Park
Caution : This datasheet can be changed without prior notice !! If you want to get up-to-date version,
please send a mail to support@pixelplus.
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
▶Features
▷762 x 504 total pixel array with
RGB bayer color filters and micro-lens.▷Power supply :
AVDD : 2.8V, HVDD : 2.8V, CVDD : 2.8V ▷Output formats :
◆Composite Output mode :
-CVBS ( NTSC/PAL ),◆Digital Output mode :
-
max. D1 (720x480) YCbCr422/RGB565/RGB444. ( progressive, 60 fps @ 54MHz )-max. D1 (720x480) Bayer
( progressive, 60 fps @ 27MHz )
◆Analog/Digital Output mode :
-ITU-R. BT656 ( 720x240/288 )( interlaced, 60 fields @ 27MHz )-CVBS ( 30 fps @ 27MHz )
▷Image processing on chip : lens shading, gamma / defect / color correction,
low pass filter, color interpolation, saturation, edge enhancement, brightness, contrast, special effects, auto black level ,
auto white balance, auto exposure control and back light compensation.
▷Frame size, window size and position can be programmed through a 2-wire serial interface bus.
▷VGA / QVGA / QQVGA / CIF / QCIF Scaling.
▷High Image Quality and Ultra low light performance.▷I2C master include.
▷Motion detection support
▷Alarm mode, Privacy mode support ▷Artificial Intelligence power save mode.▷Chip Address Selection PADs ▷Horizontal / Vertical mirroring.
▷50Hz, 60Hz flicker automatic cancellation.▷Software Reset / Power ON Reset ▷External Sync (Gen. Lock) support ▷Off-chip IR-LED control.
▷Embedded Moving IR filter switch & IRIS switch driver ▷Crystal input support.
▷On chip regulator for DVDD(1.5V)
▷CSP/CLCC/PLCC Package type supports
[Table 1] Typical Parameters
AVDD
AGND
ISIN RSTB VSYNC
nhdt-471
D9
D8
D7
D6
D5
D4
HVDD
D3
D2
HGND
健康枕
42414039383736353433323130292827
STDBY 4326SCL CADD14425SDA CADD04524DGND LED 4623HGND TE 4722HVDD GENI 48Effevtive Pixel Array
21DVDD GENO 4920SCK MIRS05019MISO MIRS15118MOSI IRIS05217CSB IRIS153
16D1
白光干涉12
3
456789101112131415
AVDD1
AGND1
CN
CP
CVDD
CGND
REXT
D0
PCLK
DVDD
HVDD
HGND
DGND
X1
X2
Notch : Bottom
Total Pixel Array 762(H) x 504(V)Effective Pixel Array 728(H) x 488(V)Pixel Size
6.35 um x
7.4 um Effective Image Area 4622.8 um x 3611.2 um Optical Format 1/3 inch Max. Clock frequency 54 MHz
Max. Frame Rate
-60fps, 720x480 YCbCr @ 54MHz -60fps, 720x480 Bayer @ 27MHz -60field, 720x240(288) YCbCr @ 27MHz
-CVBS 30 fps @ 27MHz
Dark Signal 46.7 [ mV/sec ] @60℃Sensitivity 9.67 [V/Lux.sec]Power Supply
Analog : 2.8V, HVDD : 2.8V,CVDD : 2.8V
Power Consumption
247 mW @Dynamic 392.6 uW @Standby
Operating Temp.
(Fully Functional Temp)-40~ 70[℃]Dynamic Range 63.7 [dB]SNR
46.4 [dB]
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
▶PIN Descriptions
Num NAME I/O Type PAD Description
1AVDD1P Analog VDD1 :2.8V DC.
押花材料2AGND1P Analog Ground1
3CN O Composite Differential Negative signal
(75 ohm single termination(LCD), 37.5 ohm double termination (CRT))
4CP O Composite Differential Positive signal.
(75 ohm single termination(LCD), 37.5 ohm double termination (CRT))
5CVDD P DAC power supply : 2.8V DC
6CGND P DAC power ground
7REXT I External Resistor. The resistor value can be changed by user tuning. (Typically 30k ohm when CN/CP 37.5 ohm termination, 60k ohm when CN/CP 75 ohm termination)
8D0O Bit 0 of data output
9PCLK O Pixel clock. Data can be latched by external devices at the rising or falling edge of PCLK.
The polarity can be controlled anyway.
10DVDD P Digital Power supply : In case of using on-chip digital regulator, DVDD must be tied to DGND by total 1uF bypass capacitor. Otherwise, 1.5V DC must be supplied with 100nF to DGND.
11HVDD P Digital VDD for I/O : 2.8V. Voltage range for all output signals is (0V or HVDD)
12HGND P Digital GND for I/O
13DGND P Digital GND for core
14X1I Crystal input pad or Master clock input pad
15X2O Crystal output pad *(1)
16D1O Bit 1 of data output
17CSB O Chip Select Signal for Serial Peripheral Interface(SPI)
18MOSI O Data Output for Serial Peripheral Interface(SPI)
19MISO I Data Input Signal for Serial Peripheral Interface(SPI)
20SCK O Clock Signal for Serial Peripheral Interface(SPI)
(1)In case of using External clock, crystal output pad(X2) must be floated and clock input PAD is X1.
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
PIN Descriptions(Cont.)
[Table 2] Pin Descriptions
21DVDD P Digital Power supply : In case of using on-chip digital regulator, DVDD must be tied to DGND by total 1uF bypass capacitor. Otherwise, 1.5V DC must be supplied with 100nF to DGND.
22HVDD P Digital vdd for I/O. Voltage range for all output signals is (0V~HVDD)33HGND P Digital GND for I/O 24DGND P Digital GND for core
25SDA I/O 2-wire serial interface data.26SCL I/O 2-wire serial interface clock.
27HSYNC O Horizontal synchronization pulse. HSYNC is high (or low) for the horizontal window of interest. It can be programmed to appear or not outside the vertical window of interest.28HGND P Digital GND for I/O 29D2O Bit 2 of data output 30D3O Bit 3 of data output
31HVDD P Digital vdd for I/O. Voltage range for all output signals is (0V~HVDD)32D4O Bit 4 of data output 33D5O Bit 5 of data output 34D6O Bit 6 of data output 35D7O Bit 7 of data output 36D8O Bit 8 of data output 37D9O Bit 9 of data output
38VSYNC O Vertical sync : Indicates the start of a new frame
39RSTB I System reset must remain low for at least 8 master clocks after power is stabilized. When the sensor is reset, all registers are set to their default values.40ISIN I Illumination sensor input (must be under 1.0V).
41AGND P Analog Ground
42AVDD P Analog VDD : 2.8V DC
43STDBY I Power stdby mode. When Stdby ='1', there's no current flow in any analog circuit branch,neither any beat of digital clock.
44CADD1I Chip Address selection bits [1:0], Default [11]
45CADD0I 46LED O LED provides the enable signal which can turn-on LED device when low light condition 47TE I Chip Test mode enable.
48GENI I External Frame sync input. Slave chip can receive the external frame sync signal from master chip
49GENO O External Frame sync output. Master chip can output the external frame sync signal through this pad to synchronize all digital outputs of two or more chips 50MIRS0O Moving IR/AR transition Switch control PADs
51MIRS1O 52IRIS0O IRIS control PADs
53
IRIS1
O
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel Array
▶Signal Environment
▶Chip Architecture
PC1089K has 3.3V tolerant Input pads. Input signals must be higher than or equal to HVDD but cannot be higher than 3.3V. PC1089K input pad has built in reverse current protection circuit, which makes it possible to apply input voltage even if the HVDD is disconnected or floating. Voltage range for all output signals is 0V ~ HVDD.
PC1089K has 762 x 504 total pixel array and column/row driver circuits to read out the pixel data
progressively. CDS circuit reduces noise signals generated from various sources mainly resulting from process variations. Pixel output is compared with the reset level of its own and only the difference signal is sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain factors to balance the color of images in various light conditions. The analog signals are converted to digital forms one line at a time and 1 line data are streamed out column by column. The Bayer RGB data are passed through a sequence of image signal processing blocks to finally produce YCbCr 4:2:2 output data. Image signal
processing includes such operations as gamma correction, defect correction, low pass filter, color interpolation, edge enhancement, color correction, contrast stretch, color saturation, white balance, exposure control and back light compensation. Internal functions and output signal timing can be programmed simply by modifying the register files through 2-wire serial interface.
[Fig. 2] Block Diagram
Pixel Array 762 ×504
& Sensor Core
Timing Generator
泵Bayer Processing
Image Signal Processing
FIFO
Output format BT656
Enc.FIFO
TV Enc.
DAC
Two-wire Serial Interface ( slave )
AE/AWB
External Input (BT656 format Only)
Composite Output
Parallel Output
Serial Interface ( master )
stdby
rstb x2
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