1
235114f
Simultaneous Sampling ADC
with Shutdown
The LTC ®2351-14 is a 14-bit, 1.5Msps ADC with six simultaneously sampled differential inputs. The device draws only 5.5mA from a single 3V supply, and comes in a tiny 32-pin (5mm × 5mm) QFN package. A SLEEP shutdown mode further reduces power consumption to 12µW. The combination of low power and tiny package makes the LTC2351-14 suitable for portable applications.The LTC2351-14 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These six sampled inputs are then converted at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source.The device converts 0V to 2.5V unipolar inputs differen-tially, or ±1.25V bipolar inputs also differentially,depending on the state of the BIP pin. Any analog input may swing rail-to-rail as long as the differential input range is maintained.
The conversion sequence can be abbreviated to convert fewer than six channels, depending on the logic state of the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in 96 clocks for compatibility with standard serial interfaces.
■ 1.5Msps ADC with 6 Simultaneously Sampled Differential Inputs
■250ksps Throughput per Channel ■75dB SINAD
■Low Power Dissipation: 16.5mW ■3V Single Supply Operation
■ 2.5V Internal Bandgap Reference, Can be Overdriven with External Reference
■3-Wire SPI-Compatible Serial Interface ■Internal Conversion Triggered by CONV ■SLEEP (12µW) Shutdown Mode ■NAP (4.5mW) Shutdown Mode
■0V to 2.5V Unipolar, or ±1.25V Bipolar Differential Input Range
■83dB Common Mode Rejection
■
Tiny 32-Pin (5mm × 5mm) QFN Package
■Multiphase Power Measurement ■Multiphase Motor Control ■Data Acquisition Systems电暖画
Uninterruptable Power Supplies
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Protected by U.S. Patents including 6084440, 6522187.
µF
2
LTC2351-14235114f
SYMBOL PARAMETER CONDITIONS
MIN TYP MAX UNITS
V IN Analog Differential Input Range (Notes 3, 8, 9) 2.7V ≤ V DD ≤ 3.6V, Unipolar 0 to 2.5V 2.7V ≤ V DD ≤ 3.6V, Bipolar ±1.25V V CM Analog Common Mode + Differential 0 to V DD
V
Input Range
(Note 8)
I IN Analog Input Leakage Current ●
1
µA C IN Analog Input Capacitance 13
pF t ACQ Sample-and-Hold Acquisition Time (Note 6)●
39
ns t AP Sample-and-Hold Aperture Delay Time 1ns t JITTER Sample-and-Hold Aperture Delay Time Jitter 0.3ps t SK Channel to Channel Aperture Skew 200
ps CMRR
Analog Input Common Mode Rejection Ratio
f IN = 100kHz, V IN = 0V to 3V –83dB f IN = 10MHz, V IN = 0V to 3V
–67
dB
A U G W
A W U W A R BSOLUTE
XI TI S (Notes 1, 2)
Supply Voltage (V DD , V CC , OV DD )..............................4V Analog and V REF Input Voltages
(Note 3)...................................– 0.3V to (V DD + 0.3V)Digital Input Voltages ..................– 0.3V to (V DD + 0.3V)Digital – 0.3V to (V DD + 0.3V)100mW Operation Temperature Range
<0°C to 70°–40°C to 85°C Storage –65°C to 125°C
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T A = 25°C. With internal reference, V DD = V CC = 3V.
CO VERTER CHARACTERISTICS U
A ALOG I PUT
U
W U U
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER T JMAX = 125°C, θJA = 34°C/W EXPOSED PIN IS GND (PAD 33)MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
161514131211109
25262728TOP VIEW
32-PIN (5mm × 5mm) PLASTIC QFN
29303132
1
234567824
23222120191817CH4+CH4–GND CH5+CH5–GND V REF V CC CH1–CH1+GND CH0–CH0+OV DD OGND SDO
G N D
C H 3–
C H 3+
G N D
G N D
C H 2–
C H 2+
G N D
V D D
S E L 2
S E L 1
S E L 0
B I P
C O N V
D G N D
S C K
33
LTC2351CUH-14LTC2351IUH-14
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: www.linear/leadfree/
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T A = 25°C. With internal reference, V DD = V CC = 3V.
PARAMETER
CONDITIONS
MIN TYP MAX UNITS Resolution (No Missing Codes)●
14Bits Integral Linearity Error (Note 5)●–3±13LSB Offset Error
雨水弃流井
(Note 4)
●
–4.5±1 4.5mV Offset Match from CH0 to CH5–3±0.53mV Range Error
(Note 4)
●
–12±212mV Range Match from CH0 to CH5–5
±15
mV Range Tempco
Internal Reference (Note 4)
±15ppm/°C External Reference ±1
ppm/°C
QFN PART MARKING 235114
3
LTC2351-14
235114f
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T A = 25°C. With internal reference, V DD = V CC = 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-Noise Plus 100kHz Input Signal ●7175dB Distortion Ratio 300kHz Input Signal 75dB THD Total Harmonic 100kHz First 5 Harmonics ●
–80
–90dB Distortion 300kHz First 5 Harmonics –86dB SFDR Spurious Free 100kHz Input Signal 90dB Dynamic Range 300kHz Input Signal
86dB IMD
Intermodulation 0.625V P-P , 833kHz into CH0+, 0.625V P-P , 841kHz into CH0––80dB Distortion Bipolar Mode. Also Applicable to Other Channels Code-to-Code V REF = 2.5V (Note 17)
0.7LSB RMS
Transition Noise Full Power Bandwidth V IN = 2.5V P-P , SDO = 11585LSB P-P (–3dBFS) (Note 15)50MHz Full Linear Bandwidth
S/(N + D) ≥ 68dB, Bipolar Differential Input
5
MHz
DY A IC ACCURACY
U
W I TER AL REFERE CE CHARACTERISTICS
U U U
T A = 25°C. V DD = V CC = 3V.
PARAMETER CONDITIONS MIN
TYP MAX
UNITS
V REF Output Voltage I OUT = 0
2.5V V REF Output Tempco 15ppm/°C V REF Line Regulation V DD = 2.7V to
3.6V, V REF = 2.5V 600µV/V V REF Output Resistance Load Current = 0.5mA 0.2ΩV REF Settling Time Ext C REF = 10µF
2
ms External V REF Input Range
2.55
V DD V
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T A = 25°C. V DD = V CC = 3V.
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U SYMBOL PARAMETER
CONDITIONS MIN
TYP MAX UNITS
V IH High Level Input Voltage V DD = 3.3V ● 2.4
V V IL Low Level Input Voltage V DD = 2.7V ●0.6V I IN Digital Input Current V IN = 0V to V DD
●
±10
µA C IN Digital Input Capacitance 5
pF V OH High Level Output Voltage V DD = 3V, I OUT = –200µA ● 2.5 2.9V V OL Low Level Output Voltage V DD = 2.7V, I OUT = 160µA 0.05
V V DD = 2.7V, I OUT = 1.6mA ●0.4V I OZ Hi-Z Output Leakage D OUT V OUT = 0V and V DD
●
±10
µA C OZ Hi-Z Output Capacitance D OUT 1pF I SOURCE Output Short-Circuit Source Current V OUT = 0V, V DD = 3V 20mA I SINK
Output Short-Circuit Sink Current
V OUT = V DD = 3V 15
mA
4
LTC2351-14
235114f
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T A = 25°C. V DD = 3V.
TI I G CHARACTERISTICS
U
W Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than V DD without latchup.Note 4: Offset and range specifications apply for a single-ended CH0+ –CH5+ input with CH0– – CH5– grounded and using the internal 2.5V reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Linearity is tested for CH0 only.Note 6: Guaranteed by design, not subject to test.Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference between CHx + and CHx –, x = 0–5.
Note 9: The absolute voltage at CHx + and CHx – must be within this range.Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the 96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load.Note 15: The full power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5V P-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period.Note 17: The conversion process takes 16 clocks for each channel that is enabled, up to 96 clocks for all 6 channels.
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. V DD = V CC = 3V.
POWER REQUIRE E T S
W
U SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS f SAMPLE(MAX)Maximum Sampling Frequency per Channel ●250
kHz
(Conversion Rate)
t THROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period)●4
µs t SCK Clock Period (Note 16)●
4010000
ns
t CONV Conversion Time
(Notes 6, 17)96SCLK cycles
t 1Minimum High or Low SCLK Pulse Width (Note 6)2ns t 2CONV to SCK Setup Time (Notes 6, 10)310000ns t 3SCK Before CONV
(Note 6)0ns t 4Minimum High or Low CONV Pulse Width (Note 6)4ns t 5SCK ↑ to Sample Mode (Note 6)4ns t 6CONV ↑ to Hold Mode
(Notes 6, 11) 1.2ns t 796th SCK ↑ to CONV ↑ Interval (Affects Acquisition Period)(Notes 6, 7, 13)45
ns t 8Minimum Delay from SCK to Valid Bits 0 Through 11(Notes 6, 12)8ns t 9SCK ↑ to Hi-Z at SDO
(Notes 6, 12)6ns t 10Previous SDO Bit Remains Valid After SCK (Notes 6, 12)2
ns t 11
V REF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
SYMBOL PARAMETER CONDITIONS
MIN TYP MAX UNITS
V DD , V CC Supply Voltage 2.7
3.0 3.6V I DD + I CC
Supply Current
Active Mode, f SAMPLE = 1.5Msps ● 5.58mA Nap Mode ●
1.52mA Sleep Mode
4.015
µA PD Power Dissipation
Active Mode with SCK, f SAMPLE = 1.5Msps
16.5
mW
5
LTC2351-14
235114f
OUTPUT CODE
–1D I F F E R E N T I A L L I N E A R I T Y (L S B )
–0.8–0.4–0.2010.44096
235114 G08
–0.60.60.80.2819212288
16384
SINAD vs Input Frequency
V DD = 3V, T A = 25°C
THD, 2nd and 3rd vs Input Frequency
TYPICAL PERFOR A CE CHARACTERISTICS U W
100kHz Unipolar Sine Wave 8192 Point FFT Plot
100kHz Bipolar Sine Wave 8192 Point FFT Plot
SNR vs Input Frequency
SFDR vs Input Frequency
Differential Linearity vs Output Code,Unipolar Mode
Integral Linearity vs Output Code,
Unipolar Mode
FREQUENCY (MHz)
50686256928680
74235114 G04
S F D R (d B )
0.1
10
1
FREQUENCY (MHz)
0.1
S N R (d B )
566259656871741
10
235114 G05
77FREQUENCY (kHz)
0M A G N I T U D E (d B )
–90–30–20–10050
100125
235114 G06
–110–50–70–100–40–120
–60–8025
75FREQUENCY (MHz)
566562597774
7168235114 G01
S I N A D (d B )
0.1
10
1
THD, 2nd and 3rd vs Input Frequency
FREQUENCY (MHz)
0.1
–110
T H D , 2n d , 3r d (d B )
–98–86–74–621
10
235114 G02
–50–104
–92–80–68–56
FREQUENCY (MHz)
–110
T H D , 2n d , 3r d (d B )
–98–86–74–62235114 G03
–50–104
–92–80–68–56
OUTPUT CODE
I N T E G R A L L I N E A R I T Y (L B S )
01216384
235114 G09
–1–2–44096
819212288–34
3FREQUENCY (kHz)
M A G N I T U D E (d B )
–90–30–20–10
050
100
125
235114 G07
–110–50–70–100–40–120
–60–8025
75
6
LTC2351-14
235114f
Full Scale Signal Response
V DD = 3V, T A = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS U W
CMRR vs Frequency
FREQUENCY (MHz)
–24–27M A G N I T U D E (d B )
–21–12–15–18–9
–6
–303100
1000
235114 G10
–30
10
235114 G11
FREQUENCY (Hz)
–100
C M R R (d B )
–60–20–40–800
10k 100k 1M 10M 100M 1G –120
1k
PSRR vs Frequency
Crosstalk vs Frequency
235114 G12
FREQUENCY (Hz)
–100
C R O S S T A L K (d B )
–60–20
–40–80010k 100k 1M 10M 100M 1G –120
100
1k
235114 G13
FREQUENCY (Hz)
–100P S R R (d B )
–60–20–40–80010k 100k 1M 10M 100M 1G –120
100
1k
豫公网安备41160202000603
站长QQ:729038198
关于我们
投诉建议