This X24C01 device has been acquired by IC Microsystems from Xicor, Inc.
ICmic
IC MICROSYSTEMS
TM
1K
X24C01
Serial E PROM
2
128 x 8 Bit
DESCRIPTION
The X24C01 is a CMOS 1024 bit serial E PROM, internally organized as 128 x 8. The X24C01 features a serial interface and software protocol allowing operation on a simple two wire bus.
2
•2.7V to 5.5V Power Supply •Low Power CMOS
—Active Current Less Than 1 mA —Standby Current Less Than 50 µA •Internally Organized 128 x 8
•2 Wire Serial Interface •Four Byte Page Write Mode •Self Timed Write Cycle
—Bidirectional Data Transfer Protocol
Xicor E PROMs are designed and tested for applications requiring extended endurance. Inherent data
2
retention is greater than 100 years.
—Typical Write Cycle Time of 5 ms
•High Reliability
—Endurance: 100,000 Cycles —Data Retention: 100 Years •8-Pin Mini-DIP, 8-PIN MSOP, and 8-PIN SOIC Packages
FUNCTIONAL DIAGRAM
(8) V CC (4) V SS
START CYCLE
H.V. GENERATION TIMING & CONTROL
(5) SDA
START STOP
LOGIC CONTROL LOGIC XDEC
E PROM 32 X 32
2
(6) SCL
LOAD
INC
WORD ADDRESS COUNTER R/W
YDEC 8 CK PIN DATA REGISTER
D
OUT
D
OUT ACK
3837 FHD F01
© Xicor, 1991 Patents Pending 3837-1.2 7/28/97 T1/C0/D0 SH
1
Characteristics subject to change without notice
元器件交易网b2b
X24C01
PIN DESCRIPTIONS
Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph.
SOIC/MSOP 1 2 3 4 X24C01 8 7 6 5
V CC NC
PIN CONFIGURATION
DIP PLASTIC 1 2 3 4 X24C01 8 7 6 5
NC NC
V CC NC
NC
V SS
SCL SDA
3837 FHD F02
PIN NAMES Symbol NC VSS VCC SDA SCL A.C. CONDITIONS OF TEST Input Pulse Levels
Input Rise and Fall Times Input and Output Timing Levels
NC NC
Description No Connect Ground Supply Voltage Serial Data Serial Clock
3837 PGM T01
NC
V SS
SCL SDA
3837 FHD F03
EQUIVALENT A.C. LOAD CIRCUIT
5V 2190Ο
VCC x 0.1 to VCC x 0.9
10 ns
OUTPUT
VCC x 0.5
3837 PGM T02
100pF
3837 FHD F16
2
元器件交易网b2b
X24C01
DEVICE OPERATION
模拟温度传感器The X24C01 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C01 continuously monitors the SDA and SCL lines for the start condition and will not respond to
clock for both transmit and receive operations. Therefore, the X24C01 will be considered a slave in all
applications.
any command until this condition has been met. Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
3837 FHD F06
3
元器件交易网b2b
X24C01
The X24C01 will respond with an acknowledge after recognition of a start condition, a seven bit word address and a R/W bit. If a write operation has been selected, the X24C01 will respond with an acknowledge after each
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C01 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW
byte of data is received.
In the read mode the X24C01 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the ma
ster, the X24C01 will continue to transmit data. If an acknowledge is not detected, the X24C01 will terminate further data transmissions. The master must then issue a stop condition to return the X24C01 to the standby power mode and
to acknowledge that it received the eight bits of data. Refer to Figure 3.
place the device into a known state.
Figure 2. Definition of Start and Stop
SCL
SDA START CONDITION STOP CONDITION
3837 FHD F07
Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
ACKNOWLEDGE
3837 FHD F08
木纹扣板4
元器件交易网b2b
X24C01
WRITE OPERATIONS
Byte Write To initiate a write operation, the master sends a start condition followed by a seven bit word address and a write bit. The X24C01 responds with an acknowledge, then waits for eight bits of data and then responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C01 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the X24C01 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 4 for the address, acknowledge and data transfer sequence. Page Write The most significant five bits of the word address define the page address. The X24C01 is capable of a four byte page write operation. It is initiated in the same manner as
the byte write operation, but instead of terminating the transfer of data after the first data byte, the master can
transmit up to three more bytes. After the receipt of each data byte, the X24C01 will respond with an acknowledge. After the receipt of each data byte, the two low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than four data bytes prior to generating the stop condition, the address counter will “roll over” and the previously transmitted data will be overwritten. As with the byte write operation, all
inputs are disabled until completion of the internal write cycle. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
Figure 4. Byte Write
S T
BUS ACTIVITY:
WORD A ADDRESS (n) R T S
M S
DATA n
S T
O P
SDA LINE
BUS ACTIVITY: X24C01
P
L R A S / C K B
B
W
A C K
3837 FHD F09
Figure 5. Page Write
S T
BUS ACTIVITY:
A R
WORD ADDRESS (n)
DATA n
DATA n+1
DATA n+3
鞋帮加工
S T
O P
T SDA LINE
BUS ACTIVITY: X24C01
S
M S
P
L R A S / C K B
A C
A C
A C
B
W
K
K
K
3837 FHD F10
5
元器件交易网b2b
X24C01
Figure 6. ACK Polling Sequence
WRITE OPERATION COMPLETED
Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation the X24C01 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the word address for a write operation. If the X24C01 is still busy with the write operation no ACK will be returned. If the X24C01 has completed the write operation an ACK will be returned and the controller can then proceed with the
ENTER ACK POLLING
ISSUE START
next read or write operation. READ OPERATIONS
Read operations are initiated in the same manner as write operations with exception that the R/W bit of the
word address is set to a one. There are two basic read operations: byte read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth
ACK RETURNED? ISSUE SLAVE ADDRESS AND R/W = 0
ISSUE STOP
NO
YES
NEXT OPERATION
NO
clock cycle and then issue a stop condition.
Byte Read To initiate a read operation, the master sends a start condition followed by a seven bit word address and a
read bit. The X24C01 responds with an acknowledge and then transmits the eight bits of data. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
A WRITE? YES ISSUE STOP
PROCEED
PROCEED
3837 FHD F11
Refer to Figure 7 for the start, word address, read bit, acknowledge and data transfer sequence.
Figure 7. Byte Read
S T
BUS ACTIVITY: MASTER
WORD A ADDRESS n R
S T
O P
T S
M S
SDA LINE
BUS ACTIVITY: X24C01
P
L R A S / C K B
B
W
DATA n
3837 FHD F12
固态去耦合器6
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