1.General description
The LPC1768/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1768/66/65/64 operate at CPU frequencies of up to 100 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1768/66/65/64 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,8-channel general purpose DMA controller,4UARTs,2CAN channels,2SSP controllers,SPI interface, 3 I 2C-bus interfaces, 2-input plus 2-output I 2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)with separate battery supply, and up to 70 general purpose I/O pins.
The LPC1768/66/65/64 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series.
2.Features
I ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included.
I ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
I Up to 512kB on-chip flash programming memory.Enhanced flash memory accelerator enables high-speed 100 MHz operation with zero wait states.
I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.I On-chip SRAM includes:
N 32/16kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
N Two/one 16 kB SRAM blocks with separate access paths for higher throughput.These SRAM blocks may be used for Ethernet (LPC1768/66/64 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
LPC1768/66/65/64
32-bit ARM Cortex-M3microcontroller;up to 512kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 02 — 11 February 2009
Objective data sheet
I Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S-bus, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
I Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB
masters include the CPU, General Purpose DMA controller, Ethernet MAC
(LPC1768/66/64 only), and the USB interface. This interconnect provides
communication with no arbitration delays.
I Split APB bus allows high throughput with few stalls between the CPU and DMA.
I Serial interfaces:
N Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/66/64 only).
N USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device,Host,and OTG functions.The LPC1764includes a device controller only.
N Four UARTs with fractional baud rate generation,internal FIFO,DMA support,and RS-485 support. One UART has modem control I/O, and one UART has IrDA
support.
N CAN 2.0B controller with two channels.
N SPI controller with synchronous, serial, full duplex communication and programmable data length.
N T wo SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
N T wo I2C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with multiple address recognition and monitor mode.
N One I2C-bus interface supporting full I2C-bus specification and fast mode plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
N On the LPC1768/66/65only,I2S(Inter-IC Sound)interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the
GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and
receive as well as master clock input/output.
I Other peripherals:
N70General Purpose I/O(GPIO)pins with configurable pull-up/down resistors and a new, configurable open-drain operating mode.
N12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to1MHz,and multiple result registers.The12-bit ADC can be used with the GPDMA controller.
N10-bit Digital-to-Analog Converter(DAC)with dedicated conversion timer and DMA support (LPC1768/66/65 only).
N Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input and DMA support.
N One motor control PWM with support for three-phase motor control.
N Quadrature encoder interface that can monitor one external quadrature encoder.
N One standard PWM/timer block with external count input.
N RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 64 bytes of battery-powered backup registers.
N Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of time if it enters an erroneous state.
N System tick timer, including an external clock input option.
N Repetitive interrupt timer provides programmable and repeating timed interrupts.
N Each peripheral has its own clock divider for further power savings.
I Standard JT AG test/debug interface for compatibility with existing tools. Serial Wire
Debug and Serial Wire Trace Port options.
I Emulation trace module enables non-intrusive, high-speed real-time tracing of
instruction execution.
I Integrated PMU(Power Management Unit)automatically adjusts internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
I Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
I Single 3.3V power supply (2.4V to 3.6V).
I Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
I Non-maskable Interrupt (NMI) input.
I Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, and the USB clock.
I The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
I Processor wake-up from Power-down mode via interrupts from various peripherals.
电麻机
I Brownout detect with separate threshold for interrupt and forced reset.
I Power-On Reset (POR).
I Crystal oscillator with an operating range of 1MHz to 25MHz.
I4MHz internal RC oscillator trimmed to1%accuracy that can optionally be used as a system clock.
I PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
I USB PLL for added flexibility.
I Code Read Protection (CRP) with different security levels.
I Available as 100-pin LQFP package (14× 14× 1.4 mm).
3.Applications
ccty
I eMetering
I Lighting
I Industrial networking
I Alarm systems
I White goods
I Motor control
4.Ordering information
4.1Ordering options
Table 1.
Ordering information
Type number
Package Name
Description
Version LPC1768FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1766FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1765FBD100LQFP100plastic low profile quad flat package; 100 leads; body 14× 14× 1.4 mm SOT407-1LPC1764FBD100
LQFP100
plastic low profile quad flat package; 100 leads; body 14× 14× 1.4 mm
SOT407-1
Table 2.
Ordering options
Type number Flash Total SRAM Ethernet USB CAN I 2S DAC Package Sampling LPC1768FBD100
512 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins Q2 2009LPC1766FBD100256 kB 64 kB yes Device/Host/OTG 2yes yes 100 pins Q1 2009LPC1765FBD100256 kB 64 kB no Device/Host/OTG 2yes yes 100 pins Q1 2009LPC1764FBD100
128 kB
32 kB
yes
Device only
2
no
no
100 pins
Q1 2009
气门绞刀5.Block diagram
Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1.Block diagram
SRAM 32/64 kB
ARM CORTEX-M3
TEST/DEBUG INTERFACE E M U L A T I O N T R A C E M O D U L E
ACCELERATOR FLASH 512/256/128 kB
DMA
CONTROLLER
ETHERNET CONTROLLER WITH DMA (2)
USB HOST/DEVICE/OTG CONTROLLER WITH DMA (3)
I-code bus D-code bus system bus
AHB TO APB BRIDGE 0
HIGH-SPEED
GPIO煤仓疏松机
AHB TO APB BRIDGE 1
CLOCK GENERATION,POWER CONTROL,
SYSTEM FUNCTIONS
XTAL1XTAL2
RESET
clocks and controls JT AG interface
debug port
USB PHY
SSP0
UART2/3
I2S (1)
I2C2RI TIMER TIMER2/3
EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM
QUADRATURE ENCODER
SSP1
UART0/1CAN1/2I2C0/1SPI0TIMER 0/1WDT
PWM112-bit ADC PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS 32 kHz OSCILLATOR
APB slave group 1
APB slave group 0
DAC (1)
RTC POWER DOMAIN
LPC1768/66/65/64
master
master
master 002aad944
slave
slave slave
slave
slave
ROM
slave
MULTILAYER AHB MATRIX
P0 to P4SDA2SCL2SCK0SSEL0MISO0MOSI0SCK1SSEL1MISO1MOSI1RXD2/3TXD2/3PHA, PHB INDEX
EINT[3:0]
AOUT MC0A/B MC1A/B MC2A/B MCFB1/2MCABORT 4 × MAT22 × MAT32 × CAP22 × CAP33 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1RTCX2VBAT
PWM1[7:0]2 × MAT0/12 × CAP0/1
RD1/2TD1/2SDA0/1SCL0/1AD0[7:0]
SCK/SSEL MOSI/MISO 8 × UART1
RXD0/TXD0P0, P2PCAP1[1:0]RMII pins USB pins
CLKOUT
M P U
(1)LPC1768/66/65 only (2)LPC1768/66/64 only
铝槽钢(3)LPC1764 USB device only
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