Default Switch and Jumper Settings The default switch and jumper settings for the ZC706 evaluation board are provided in this appendix.
jumper2
AA19 respectively, enabling the user to implement their own fan speed control IP in the SoC PL logic.
More information about the power system components used by the ZC706 evaluation board are available from the Texas Instruments digital power website [Ref33].
XADC Analog-to-Digital Converter
[Figure1-3, callout 33]
The XC7Z045 SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480) for details on the capabilities of the analog front end. Figure1-38 shows the XADC block diagram.
Figure 1-38:XADC Block Diagram
Figure 1-39:XADC Header (J63)
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以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7Z045-2FF900I的详细参数，仅供参考 Jumpers
18J72MIO Select Header MIO4 (Note: DIP SW11 pole 3 affects this signal)
1-2QSPI0_IO4 = MIO2_SELECT 1519J73MIO Select Header MIO5 (Note: DIP SW11 pole 4 affects this signal)
1-2QSPI0_IO5 = MIO2_SELECT 1520
J74
MIO Select Header MIO6 (Note: DIP SW11 pole 5 affects this signal)
1-2
QSPI0_CLK = MIO6_SELECT
15
HDR_1X 3
21J43PS_SRST_B Select Header 1-2PS_SRST_B = PS_SRST_B_SW (MAX16025 U8 pin 10)1522J44PS_POR_B Select Header
1-2PS_POR_B = PS_POR_B_SW (MAX16025 U8 pin 11)1523J45U51 Ethernet PHY CONFIG3 pin 3 1K pull-up to 1.8V or 1 K Ω pull-down to GND Select Header 1-2U51 pin 3 CONFIG3 = 1 (p/u to 1.8V)
2924J46U51 Ethernet PHY CONFIG2 pin 2 tie to 1.8V or LED0 Select Header
OPEN J9 sets U51 pin 2 CONFIG2 condition
2925
J47
U51 Ethernet PHY CONFIG3 pin 3 LED1 or LED0 Select Header
OPEN
No connection to LED0 or LED1, J45 sets U51 pin 3 CONFIG3 condition 29
26J48U12 USB3320 2.0 MODE Select Header
2-3HOST/OTG Mode selected 3127J49USB 2.0 Micro-B connector J2 ID pin 4 function Select Header
1-2J2 ID pin 4 connected to USB3320 U12 pin 23 ID 3128J50USB_VBUS_SEL 1uF/120 uF capacitor to GND Select Header
2-3USB_VBUS_SEL net has 120 uF to GND
3129J51USB 2.0 Micro-B connector J2 ID shield pins connection Select Header
1-2J2 shield pins to GND 3130J52XADC_VREFP source Select Header 1-2XADC_VREFP = XADC_VREF 3531J53XADC_VCC source Select Header 1-2XADC_VCC = VCCAUX 1.8V 3532J54U38 REF3012 VREF Vin Select Header 2-3U38 powered by XADC_VCC (U14 1.85V)
3533J55SPF+ P2 SFP_RS1 BW Select Header 2-3LOW BW TX selected 4134
J56
SPF+ P2 SFP_RS0 BW Select Header
2-3
LOW BW RX selected
41
Table A-2:Default Jumper Settings (Cont’d)
Jumper Callout
Jumper Function
Default Jumper
Position
Option Selected
Schematic 0381513 Page
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