1. GENERAL DESCRIPTION
The LH220Q32 is a Color Active Matrix Liquid Crystal Display with Light Emission Diode(LED) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is transflective type display operating in the normally white mode. This TFT-LCD has 2.2 inch diagonally measured active display area with (320*RGB*320) resolution. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
渗透印章Block Diagram
Touch
Panel
Mating User Connector: Hirose FH23-39S-0.3SHW(05)
Fig 1.1 Block Diagram of TFT-LCD Module with LED Backlight Unit
Notes:
方形
气囊1. Applies to VDD, RESET, PCLK, HSYNC, VSYNC, LCD_ON, PCI, Data.2. Applies to each LED individually.
3. Allowable forward current is refer to Fig 2.1
2. ABSOLUTE MAXIMUM RATINGS
The following are maximum values which, if exceeded, may cause faulty operation or damage to the unit.
2, 3
mA
一水氢氧化锂
30
-I LED
LED Current
2mW
120-P LED LED Power Consumption 1V 4.2-0.3V DD Power Supply Input Max Min.Notes Units Values
Symbol Parameter
Ambient Temperature Ta[°C]
Fig 2.1 Ambient Temperature vs. Allowable Forward Current
Table 2.1 Absolute Maximum Ratings
1mA
19.5
12
Ivdd
Current Consumption, Panel
V V V Units 22Notes
0.2V DD -0
V IL “L”Level Input Voltage V DD -0.8 V DD
V IH “H”Level Input Voltage 3.13.02.9V DD LCD Power Supply Voltage Max Typ.Min Values
Symbol Parameter
3. ELECTRICAL SPECIFICATIONS 3-1. ELECTRICAL CHARACTERISTICS
Notes:
1. The specified current consumption are under the conditions at V DD = 3.0V, Ta=25°
C, and fv=54 Hz,16 gray steps is displayed and fv is the frame frequency.
2. Input mode of Data, PCLK,HSYNC,VSYNC,LCD_ON,PCI,RESET.
3-2. BACK LIGHT UNIT
The edge-lighting type of back light unit consists of 3 LEDs which is connected in serial.
mW
V mA Units Notes
137
125
-
P LED
LED Power Consumption
10.59.6-
V LED LED Forward Voltage 3013-I LED LED Current Max Typ.Min Values
Symbol Parameter
Table 3.1 Electrical Characteristics Of TFT-LCD Module
Table 3.2 Electrical Characteristics Of Back Light Unit
3-3. TOUCH PANEL
(GND=0V, Ta=25℃)X-axis Ω1100-100Y-axis Ω1100-100Terminal Resistance %1.5--1.5Linearity
DC
V 75-Voltage DC 25V ㏁
--20Insulation Resistance Remarks
Unit Max.Typ.Min.Parameter %
-80
78
Transparency
DC 5V, 100㏀
ms 20--Chattering Table 3.3 Touch Panel Electrical and Optical Specifications
3-4. INTERFACE CONNECTIONS
展频原理
Ground reference (0V)Power Vss 37Digital Power Supply (3.0V)Power V DD 35Ground reference (0V)Power Vss 36Ground reference (0V)Power Vss 38LED Anode I LED_Anode 32LED Cathode
I LED_Cathode
33Ground reference (0V)Power Vss 34Red Data
I R216Red Data / ID Bit 1I/O R1/ID117Ground reference (0V)
Power Vss 18Green Data I G519Green Data I G420Green Data I G321Green Data I G222Green Data I G123Green Data
I G024Ground reference (0V)
Power Vss 25Blue Data I B526Blue Data I B427Blue Data I B328Blue Data
I B229Blue Data / ID Bit 2I/O
B1/ID230Switches LCD on (active low)I LCD_ON 31Vss
R3R4R5Vss VSYNC HSYNC Vss PCLK Vss PCI RESET X_Right Y_Top X_Left Y_Bottom SYMBOL Ground reference (0V)
Red Data Red Data Red Data Ground reference (0V)
Vertical Sync Signal Horizontal Sync Signal Ground reference (0V)Pixel Clock
Ground reference (0V)
Power Control In LCD Reset Touch Panel X-Right
Touch Panel Y-Top Touch Panel X-Left Touch Panel Y-Bottom Comment
Power
39
I 15I 14I 13Power 12I 11I 10Power 9I 8Power 7I 6I 5Analog 4Analog 3Analog 2Analog 1I/O, Power, Analog
Pin The pin connections are provided in Table 3.3 The mating connector for the flex tail is Hirose FH23-39S-0.3SHW(05) Or equivalent.
Table 3.4 Module Connector Pin Configuration
ns --80tCYCD PCLK cycle time ns
ns ns ns clk line line line line dots dots clk dots ns ns ns ns line dots ns ns MHz KHz Hz V V Unit
2
100
-
-
tfsclk
Slow clock fall time
2100--trsclk Slow clock rise time 125--trgbf Fast clock fall time 125--trgbr Fast clock rise time 100-4-5tvhde Vsync falling edge Hsync falling edge 864tvfp Vsync front porch -8-tvbp Vsync falling edge 1st data start 161412tvblk Vertical blanking period 336334332
Number of vertical 23.515.57.5thfp
Hsync front porch -24.5-thbp Hsync falling edge 1st data start 484032thblk Horizontal blanking perio
d
368360352
嫁接刀Number of Horizontal --20tPDH
Data hold time --20tPDS Data setup time --20tSYNCH Hsync hold time --20tSYNCS Hsync setup time 411thsw Vsync low pulse width 854thsw Hsync low pulse width -0.5tclk 32PW DL ,PW DH PCLK Low/High pulse width
160154148tclk PCLK pulse width 6.756.56.25ftch PCLK frequency 19.218.117.0fh Horizontal frequency 57.854.150.5fv Vertical frequency VDD -0.8*VDD V IH 0.2*VDD 0-0.3V IL Input clock voltage Note
Maximum
Typical
Minimum
Symbol
Item
Notes: 1. PCLK, VSYNC, HSYNC
2. LCD_ON, PCI Table
3.5 Timing Parameters
3-5. SIGNAL TIMING SPECIFICATIONS
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