220GHz f T and 400GHz f max in 40-nm GaN DH-HEMTs
with Re-grown Ohmic
K. Shinohara, A. Corrion, D. Regan, I. Milosavljevic, D. Brown, S. Burnham, P. J. Willadsen, C. Butler, A. Schmitz, D. Wheeler, A. Fung†, and M. Micovic HRL Laboratories, LLC, 3100 Malibu Canyon Road, Malibu, CA 90265-4797, USA
†Jet Propulsion Laboratory, 4800 Oak Grove Drive, Pasadena, CA 91109, USA
Phone: +1-310-317-5093, Fax: +1-310-317-5485, E-mail: kshinohara@hrl
Abstract
We report record RF performance in 40nm-gate GaN-HEMT technology. Through vertical scaling in an AlN/GaN/AlGaN double heterojunction (DH) HEMT structure and reduction of access resistance using MBE re-growth of n+-GaN ohmic contacts, fully-passivated 40-nm devices exhibited excellent DC characteristics, such as an R on of 0.81Ω·mm, an I dmax of 1.61A/mm, a BV off of 42V, and a peak extrinsic g m of 723mS/mm, resulting in a peak f T of 220GHz and a peak f max of 400GHz. The measured f T and f max are the highest ever reported in a GaN-HEMT technology. Small signal model
and delay time analysis showed that the parasitic charging time was only 10% of total delay time and the gate transit time scaled with the gate length (L g) down to 40nm, demonstrating high scalability of the new technology.
Introduction
GaN-based materials offer significant potential for high-frequency high-power HEMTs due to their high electron velocity and high critical field. The high density of states in GaN, the polarization doping effect at GaN/Al(Ga)N hetero-interfaces, and the wide band-gap of Al(Ga)N are great advantages for vertical device scaling for high frequency operation. AlN offers the greatest potential as a scalable barrier material among Al x Ga1-x N alloy compositions due to its large bandgap and polarization effects. However, a resulting high potential barrier for electrons makes it difficult to form a low resistance ohmic contact to the channel. In this paper, we combined the advantages of an AlN barrier with a low resistance ohmic contact by fabricating AlN/GaN/AlGaN DH-HEMTs with re-grown n+-GaN ohmic contacts by MBE.
Device design
Fig. 1 illustrates the technology cross-section. The DH-HEMT structure was grown on a 3inch semi-i
nsulating SiC substrate by MBE. The epitaxial structure consisted of a GaN(2.5nm)/AlN(3.5nm) top barrier, a GaN(20nm) channel, and an Al0.08Ga0.92N back barrier. The thin GaN/AlN top barrier minimized the gate-to-channel distance while maintaining a high 2DEG density and a low gate leakage current. The Al0.08Ga0.92N back barrier was employed to increase carrier confinement, suppressing the short channel effect [1]. A high 2DEG density (n s) of 1.3×1013cm-2 and high mobility (µ) of 1200cm2/V·s were measured after surface passivation by SiN. The GaN/AlN layer in the ohmic regions was etched into the GaN channel layer by Cl2-based RIE followed by MBE re-growth of highly-Si-doped n+-GaN (50nm, 7×1019cm-3). Source-drain electrodes were formed using non-alloyed Ti/Pt. An extremely low access resistance (R ac) of 0.08ohm·mm defined as the resistance between the ohmic metal and the 2DEG as shown in Fig. 1 and a 2DEG sheet resistance (R sh) of 440 ohm/sq. were measured by TLM. Pt/Au T-shaped gates with L g ranging from 200 to 40nm were fabricated using a tri-layer e-beam lithography technique. Finally, devices were passivated with 50nm of PECVD SiN.s11348
Fig. 1. Technology cross-section of a fully-passivated 40nm-gate AlN/GaN/AlGaN DH-HEMT with n+-GaN ohmic contacts regrown by MBE. Extremely small access resistance (R ac) of 0.08ohm·mm and 2DEG sheet resistance (R sh) of 440ohm/sq. were measured by TLM.
Results and Discussion
Fig. 2 shows output characteristics of a 40nm DH-HEMT with an extremely low R on of 0.81Ω·mm, an I dmax of 1.61A/mm, and an off-state breakdown voltage BV off of 42V. The device had a V th of -1.75V and a peak extrinsic g m of 723mS/mm at V ds=6V (Fig. 3). Fig. 4 shows an increase of the extrinsic g m from 672 to 723mS/mm and a small V th shift of -0.5V with reduction of L g from 200 to 40nm, implying
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an enhanced electron velocity for shorter L g with suppressed short-channel effect. S-parameter measurements were carried out in the frequency range of 0.5-67GHz and 140-220GHz. f T /f max =220/289GHz (V ds =2V) and f T /f max =186/400GHz (V ds =6V) were obtained by extrapolating |h 21|2 and U g using -20dB/decade slope after pad de-embedding (Fig. 5). Extrinsic f T /f max before pad de-embedding were 184/283 GHz at V ds =2V. At V ds =6V, MAG of 5.4dB was measured at 200GHz. For comparison, the highest f T and f max reported so far for GaN transistors are 190GHz [2] and 300GHz [3]. In Fig. 6, measured f T , f max and S-parameters are compared with a simulation using a small signal equivalent circuit model. Excellent agreement between the measurement and the simulation confirms the measured f T and f max values. It is seen that the higher f max at V ds =6V resulted from the increased voltage gain (g m /g d ) and the decreased C g
d .
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1.61.8
2.0
I d s (A /m m )
V ds (V)
Fig. 2. DC I ds -V ds characteristics of a 40-nm DH-HEMT showing an extremely small on-resistance (R on ) of 0.81ohm·mm and a maximum drain current (I dmax ) of 1.62A/mm. Off-state breakdown voltage (BV off ) of 42V was measured at a V gs of -3V.
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I d s (A /m m ) & g m (S /m m )
V gs (V)
Fig. 3. I ds and g m vs. V gs measured at V ds =2, 4, 6V for a 40-nm DH-HEMT showing an extrinsic peak g m of 723mS/mm at V ds =6V. V th is defined as a V gs linearly extrapolated from I ds -V gs curve.
0100200300400500600700800900
1000Gate length L g (nm)
P e a k g m (m S /m m )
-2.5-2.0
-1.5
-1.0
-0.5
0.0
www.auau66.ComT h r e s h o l d v o l t a g e V t h (V )
Fig. 4. Peak g m and V th vs. L g measured at V ds =6V. Increased g m and small V th
R F g a i n s (d B )
with g T ds gs V gs =-1.5V (right). f T U g using -20dB/decade
Fig. 6. Excellent agreement between measured and simulated f T /f max (at V ds =2V, V gs =-1.25V and V ds =6V, V gs =-1.5V) and S-parameters (at V ds =2V, V gs =-1.25V) using a small signal equiv
alent circuit model with parameters shown in the table.
网络滤波器
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Fig.
V ds =g m
f T & f m a x (G H z )
Fig. 7.
f m a x (G H z )
f T (GHz)
嵌入式终端
Fig. 8. Comparison of measured f T and f max with the state-of-the-art results reported for GaN-HEMT technology demonstrating large increase of both f T and f max in our devices. It is noted that the outstanding performance was obtained in fully-passivated devices.
parasitic delay. To assess delay time components, intrinsic delay time deduced by (1/2πf T )-(R s +R d )·C gd was plotted as a function of inverse drain current density [=W g /I ds ] (Fig. 10) and voltage across the channel under the gate [=V ds -I ds ·(R s +R d )] (Fig. 11). Fig. 12 shows the total delay time divided into parasitic charging, channel charging, drain delay and gate transit time for 80nm (at V ds =2V) and 40nm (at V ds =2, 4, 6, 8V) devices, illustrating that the parasitic charging time was just 10% of total delay time for the 40nm device at V ds =2V, the drain delay time increased with V ds as 0.045ps/V, and the gate transit time was nearly independent of V ds . Fig. 13 depicts the depe
ndence of delay times measured at V ds =2V on L g , showing proportional scaling of the gate transit time with the L g down to 40nm. The average electron velocity deduced from the slope was 1.1×107cm/s.
P e a k f T (G H z )
Fig. 9. f
01
2
I n t r i n s i c d e l a y t i m e (p s )
W g / I d (mm/A)
Fig. 10. Intrinsic delay time [=(1/2πf T )-(R s +R d )·C gd ] as a function of inverse drain current density for a 40-nm DH-HEMT measured at V ds =2, 4, 6, 8V.
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01
2
I n t r i n s i c d e l a y t i m e (p s )
V ds - I ds ·(R s +R d ) (V)
Fig. 11. Intrinsic delay time as a function of voltage across the channel under the gate [=V ds -I ds ·(R s +R d )] for a 40-nm DH-HEMT.
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1.4D e l a y t i m e (p s )
g g
f T =
Fig. 12. Delay time components for 80- and 40-nm DH-HEMTs showing constant gate transit time and growth of drain delay with V ds .
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D e l a y t i m e (p s )
Gate length L g (nm)
Fig. 13. Gate transit time scales proportionally with L g down to 40nm while other components are nearly independent of L g .
Conclusion
A record f T of 220GHz and a record f max of 400GHz were demonstrated for 40nm-gate AlN/GaN/
AlGaN DH-HEMTs with re-grown n +-GaN ohmic contacts. The new technology addressing aggressive vertical epi scaling, lateral L g scaling, and parasitic reduction drastically improved intrinsic device properties such as g m , voltage gain (g m /g d ) and gate capacitances while simultaneously reducing parasitic charging delay. Proportional scaling of the gate transit time with L g down to 40nm was demonstrated.
Acknowledgment
This work was sponsored by the Defense Advanced Research Projects Agency Microsystems Technology Office (DARPA-MTO) Nitride Electronic NeXt-Generation Technology (NEXT) program under DARPA/CMO Contract No. HR0011-09-C-0126, program manager Dr. John Albrecht, and DARPA/MTO COR James Sewell, AFRL/WPAFB. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressly or implied, of the Defense Advanced Research Projects Agency or the U.S. Government. (Approved for Public Release, Distribution Unlimited)
Reference
[1] M. Micovic et al ., IEDM Tech. Dig ., pp. 807-810, 2004.
[2] M. Higashiwaki, T. Mimura, and T. Matsui, Applied Physics Express , 1, 021103, pp. 1-3, 2008.
[3] J. W. Chung, W. E. Hoke, E. M. Chumbes, and T. Palacios, IEEE Electron Device Lett., 31, 3, pp. 195-197, 2010.
[4] K. Shinohara et al ., DRC Tech. Dig ., pp. 167-168, 2009.
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