SPCA514A
Digital Audio USB Controller 1. General description
The chip provides a built-in 8051 CPU with USB interface to handle three types of flash memory: NAND-type, SPI and NextFlash. It can co-operate with Digital Audio processing chip to manage the flash memory and to communicate with the PC.
2. Feature
!Build-in 8032 micro-controller and 1K bytes Data RAM
!Support USB bus with built-in transceiver
功率变送器原理!Four USB pipes supported, including default control pipe, bulk-in pipe, bulk-out pipe and interrupt pipe !Support 2M / 4M / 8M x 8 bit NAND-type Flash memory
!Hardware generated ECC code for flash memory access
!Support SPI and NextFlash serial interface
!Support SPCA751 interface
! 100-pin LQFP
3. Function description
3.1. block diagram
3.2. Embedded micro-controller
The SPCA514A has integrated an 8032-compatible micro-controller, a serial communication port and a build-in 1K SRAM. To simplify the firmware development, the users may disable the internal micro-controller and connect the SPCA514A to an external micro-controller. The following diagrams show how to connect the SPCA514A to other components when using internal micro-controller and external micro-controller.
The micro-controller is similar to DS80C320(Dallas Semiconductor) in terms of hardware features and instruction cycle timing. However, there are some important differences between the micro-controller and the DS80C320.
S e r i a l p o r t s
The micro-controller does not implement serial port framing error detection and does not implement slave address comparison for multiprocessor communications.
T i m e r2
The micro-controller does not implement timer2 down-counting mode or the down-count enable bit(T2MOD, bit0). The timer2 overflow output is active for one clock cycle. In the DS80C320, the timer2 overflow output is a square wave with a 50% duty cycle.
W a t c h d o g t i m e r
The micro-controller does not implement an internal watchdog timer.
P o w e r f a i l d e t e c t o r
The micro-controller does not implement an internal power fail detector.
S t o p m o d e
uv喷涂工艺The micro-controller internal cycle counter is reset in stop mode. The micro-controller exits stop mode only when reset.
T i m e d a c c e s s p r o t e c t i o n
T h e m i c r o-c o n t r o l l e r d o e s n o t i m p l e m e n t t i m e d a c c e s s p r o t e c t i o n.
3.3. USB Pipes
SPCA514A supports the following four USB pipes.
Default pipe (EP0): process the standard and vendor commands.
INTERRUPT-IN pipe (EP1): transmit device events (interface 0)
BULK-IN pipe (EP2): upload data to the PC (interface 0)
BULK-OUT pipe (EP3): download data and ROM code (interface 0)
All standard commands, except the Get Descriptor command, are processed by hardware. For Get Descriptor command and vendor commands, the USB controller latches
the 8-byte commands in the EP0 FIFO and interrupts the micro-controller. The micro-controller then read the 8-byte command, decodes it, and prepares the appropriate data according to the command if necessary. The data, if any, is then sent to the USB bus by the USB controller.
USB Packet Format
U S B V e n d o r C o m m a n d f o r R e g i s t e r R e a d/W r i t e(f o r e x a m p l e)
Command bmReqType BRequest wValue WIndex wLength
R e a d0C10x00reserved address1
Write0x410x00High byte :
address0
reserved
low byte:
write value
U S B B u l k-I N P a c k e t F o r m a t
The maximum packet size is fixed at 64 bytes. The size of each Bulk-IN packet is either maximum or zero. The zero-padding is applied to the last packet to make the size maximum if necessary.
U S B B u l k-O U T P a c k e t F o r m a t
The maximum packet size is fixed at 64 bytes. The size of each Bulk-OUT packet must be maximal.
U S B I n t e r r u p t-I N P a c k e t F o r m a t
The maximum packet size is fixed at two bytes. The micro-controller must program the interrupt pipe registers (both register 0x8506 and 0x8507) after it detects a new event. The USB controller sends the interrupt data to the host only after register 0x8507 is written.
3.4. Flash Memory
The flash memory is used to store data. The CPU can transfer command, address and data to the flash memory by the 8-bit I/O port. There are three operation modes for the CPU to read/write the flash memory: one is the direct mode, another is the FIFO mode and the other is pseudo DRAM mode. The ECC that is 22-bit code for every 256 bytes will
be generated in the FIFO mode. The ECC generated by hardware can be read from the registers (3 bytes for 256 bytes/page and 6 bytes for 512 bytes/page). The read/write operation sequence is described as follows.
set the flash memory chip enable
set the flash memory command enable (0X8400)
write command to the flash memory via the flash memory data register (0X8400)
clear the flash memory command enable
set the flash memory address enable
纳米除臭装置write address to the flash memory via the flash memory data register (0X8400) clear the flash memory address enable
wait the flash memory ready
D i r e c t m o d e:
read/write data from/to the flash memory via the flash memory data register (0X8400) read/write additional data from/to the flash memory via the flash memory data register (0X8400)
F I F O m o d e:
9. read/write data from/to the flash memory via the post buffer data register (0X8300)
10. read the ECC generated by hardware from the ECC registers不锈钢镀钛
11. read/write additional data from/to the flash memory via the flash memory register (0X8400)
P s e u d o D M A m o d e:
9. read the post buffer and write to the flash memory or read the flash memory and write to the post buffer via the post buffer data register (0X8300)
10. read the ECC generated by hardware from the ECC registers
read/write additional data from/to the flash memory via the flash memory register (0X8400)
P.S.
1. The additional data means the data stored in the last 8 or 16 bytes of a page in the flash memory. The size is 8 or 16 bytes based on that the page size is 256/512 bytes.
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