UBA2014
600 V driver IC for HF fluorescent lamps
Rev. 04 — 16 October 2008Product data sheet
1.General description
The IC is a monolithic integrated circuit for driving electronically ballasted fluorescent
lamps, with mains voltages up to 277V(RMS) (nominal value).
The circuit is made in a 650V Bipolar CMOS DMOS (BCD) power-logic process.
It provides the drive function for the two discrete power MOSFETs.
Besides the drive function, the IC also includes the level-shift circuit, the oscillator
function, a lamp voltage monitor, a current control function, a timer function and
protections.
2.Features
I Adjustable preheat time
I Adjustable preheat current
I Current controlled operating
I Single ignition attempt
I Adaptive non-overlap time control
I Integrated high-voltage level-shift function
I Power-down function
I Protection against lamp failures or lamp removal
I Capacitive mode protection
3.Applications
I The circuit topology enables a broad range of ballast applications at different mains
voltages for driving lamp types from T8,T5,PLC,T10,T12,PLL and PLT,for example.
NXP Semiconductors
UBA2014
600 V driver IV for HF fluorescent lamps
4.Quick reference data
5.Ordering information
Table 1.Quick reference data
V DD =13V; V FVDD −V SH =13V; T amb =25°C; all voltages are referenced to GND; see test circuit of Figure 8; unless otherwise specified.Symbol Parameter
Conditions
Min
Typ
Max
Unit
Start-up state V DD(stop)oscillator stop supply voltage
8.69.19.6V V DD(start)oscillator start supply voltage
12.413.013.6V I DD(start)
oscillator start-up supply current
V DD <V DD(start)
-170
单齿辊破碎机
200
µA
High-voltage supply V HS high-side supply voltage I HS <30µA --570V Reference voltage
V VREF reference voltage
I L =10µA
2.86 2.95
3.04V Voltage controlled oscillator
f max maximum bridge frequency 90100110kHz f min minimum bridge frequency 38.940.542.1kHz High-side output driver
I o(source)output source current V GH −V SH =0 V 135180235mA I o(sink)output sink current V GH −V SH = 13V 265330415mA Preheat current sensor V ph preheat voltage 0.570.600.63V Lamp voltage sensor
V lamp(fail)lamp fail voltage 0.770.810.85V V lamp(max)maximum lamp voltage 1.44 1.49 1.54V Average current sensor
V offset offset voltage V CSP =V CSN =0V to 2.5V −20+2mV g m
环丙基硼酸
transconductance f =1kHz 1900
3800
5700
µA/mV
Preheat timer t ph preheat time
C CT =330nF;R IREF =33k Ω 1.6 1.8 2.0s V OL LOW-level output voltage - 1.4-V V OH
HIGH-level output voltage
- 3.6
-V
Table 2.
Ordering information
Type number
Package Name
Description
Version UBA2014T SO16plastic small outline package; 16leads; body width 3.9mm SOT109-1UBA2014P
DIP16
plastic dual in-line package; 16leads (300 mil); long body
SOT38-1
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UBA2014_4© NXP B.V . 2008. All rights reserved.
Product data sheet Rev. 04 — 16 October 20083 of 19
NXP Semiconductors
UBA2014
600 V driver IV for HF fluorescent lamps
6.Block diagram
Fig 1.Block diagram
mgw579
DRIVER LOGIC
LEVEL SHIFTER
BOOTSTRAP
FREQUENCY CONTROL
AVERAGE CURRENT SENSOR
CSP 15GH 10FV DD
9
CSN
16
LOGIC
LAMP VOLTAGE SENSOR
VOLTAGE CONTROLLED OSCILLATOR
REFERENCE CURRENT
I V
GL LS
DRIVER
HS
DRIVER
6
SH 11
ACM
PREHEAT TIMER
STATE LOGIC
• reset state • start-up state • preheat state • ignition state • burn state • hold state
• power-down state
SUPPLY
V DD V REF
reset
V DD(L)
V pd
reference voltages digital analog
supply (5 V)
3 V
7
14LOGIC
轮椅电机
C O U N T E R
1
4CT
IREF
3CF
13LVS
2
CSW
5
GND
V lamp(fail)
V lamp(max)
ANT/CMD
UBA2014
PCS
8
PCS
L O G I C
7.Pinning information
7.1Pinning
7.2Pin description
Fig 2.Pin configuration (SO16)Fig 3.Pin configuration (DIP16)
UBA2014T
CT CSN CSW CSP CF VREF IREF LVS
GND ACM GL SH V DD GH PCS
FV DD
001aad405
1234
5678
109
121114131615UBA2014P
CT CSN CSW CSP CF VREF IREF LVS
GND ACM GL SH V DD GH PCS
FV DD
001aad486
1234
5678
109
121114131615Table 3.Pin description
Symbol Pin Description CT 1preheat timer output
CSW 2input of voltage controlled oscillator CF 3voltage controlled oscillator output IREF 4internal reference current input GND 5ground
GL 6gate output for the low-side switch V DD 7low-voltage supply
PCS 8preheat current sensor input
FV DD 9floating supply voltage; supply for high-side switch GH 10gate output for the high-side switch SH 11source for the high-side switch ACM 12capacitive mode input LVS 13lamp voltage sensor input VREF 14reference voltage output
CSP 15positive input for the average current sensor CSN
16
negative input for the average current sensor
8.Functional description
8.1Start-up state
Initial start-up can be achieved by charging the low-voltage supply capacitor C7
(see Figure8)via an external start-up resistor.Start-up of the circuit is achieved under the
condition that both half bridge transistors TR1 and TR2 are non-conductive. The circuit
will be reset in the start-up state. If the low-voltage supply (V DD) reaches the value of
V DD(start)the circuit will start oscillating.A DC reset circuit is incorporated in the High-Side
(HS) driver. Below the lockout voltage at the FV DD pin the output voltage (V GH−V SH) is
zero. The voltages at pins CF and CT are zero during the start-up state.
8.2Oscillation
The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the V CF(high) level and 0V. The frequency of the sawtooth is
determined by capacitor C CF, resistor R IREF, and the voltage at pin CSW. The minimum
and maximum switching frequencies are determined by R IREF and C CF; their ratio is
internally fixed. The sawtooth frequency is twice the half bridge frequency. The UBA2014
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately50%.An overview of the oscillator signal and driver signals is illustrated in
Figure4. The oscillator starts oscillating at f max. During the first switching cycle the
Low-Side (LS) transistor is switched on. The first conducting time is made extra long to
enable the bootstrap capacitor to charge.
8.3Adaptive non-overlap
The non-overlap time is realized with an Adaptive Non-overlap circuiT(ANT).By using an
adaptive non-overlap circuit,the application can determine the duration of the non-overlap
time and make it optimum for each frequency; see Figure4. The non-overlap time is
determined by the slope of the half bridge voltage, and is detected by the signal across
resistor R16 which is connected directly to pin ACM. The minimum non-overlap time is
internally fixed. The maximum non-overlap time is internally fixed at approximately 25%
of the bridge period time. An internal filter of 30ns is included at the ACM pin to increase
the noise immunity.
8.4Timing circuit
A timing circuit is included to determine the preheat time and the ignition time.The circuit
consists of a clock generator and a counter.
The preheat time is defined by C CT and R IREF and consists of 7pulses at C CT; the
maximum ignition time is 1pulse at C CT. The timing circuit starts operating after the
start-up state, as soon as the low supply voltage (V DD) has reached V DD(start) or when a
critical value of the lamp voltage (V lamp(fail)) is exceeded. When the timer is not operating汽车门把手
C CT is discharged to 0V at 1mA.
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