摘要
随着机器视觉的广泛应用，以及工业4.0和“中国制造2025”的提出，在数字图像的采集、传输、处理等领域也提出了越来越高的要求。传统的基于ISA接口、PCI接口、串行和并行等接口的图像采集卡已经不能满足人们对于高分辨率、实时性的图像采集的需求了。一种基于FPGA和USB3.0高速接口，进行实时高速图像采集传输的研究越来越成为国内外在高速图像采集研究领域的一个新的热点。 金属规整填料
针对高速传输和实时传输这两点要求，通过采用FPGA作为核心控制芯片与USB3.0高速接口协调工作的架构，实现高帧率、高分辨率、实时性的高速图像的采集和传输，并由上位机进行可视化操作和数据的保存。整体系统采用先硬件后软件的设计方式进行设计，并对系统各模块进行了测试和仿真验证。通过在FPGA 内部实现滤波和边缘检测等图像预处理操作，验证了FPGA独特的并行数据处理方式在信号及图像处理方面的巨大优势。 在系统硬件设计部分，采用OV5640传感器作为采集前端，选用Altera的Cyclone IV E系列FPGA作为系统控制芯片，由DDR2存储芯片进行数据缓存，采用Cypress公司的USB3.0集成型USB3.0芯片作为数据高速接口，完成了各模块的电路设计和采集卡PCB实物制作。
系统软件设计，主要分为FPGA逻辑程序部分、USB3.0固件程序部分和上位机应用软件部分。通过在FPGA上搭建“软核”的方式，由Qsys系统完成OV5640的配置和初始化工作。由GPIF II接口完成FPGA和
FX3之间的数据通路。通过编写状态机完成Slave FIFO的时序控制，在Eclipse中完成USB3.0固件程序的设计和开发。上位机采用VS2013软件通过MFC方式设计，从而完成整体图像采集数据通路，并在上位机中显示和保存。
整体设计实现预期要求，各模块功能正常，USB3.0传输速度稳定在320MB/s，通过上位机保存至PC机硬盘的图像分辨率大小为1920*1080，与传感器寄存器设置一致，采集卡图像采集帧率为30fps，滤波及边缘检测预处理符合要求，采集系统具有实际应用价值和研究意义。
关键词：FPGA；USB3.0；高速传输；图像处理；SOPC
ABSTRACT
With the wide application of machine vision, and the proposal of Industry 4.0 and "Made in China 2025," higher and higher requirements are also raised in the fields of digital image acquisition, transmission, and processing. The traditional image acquisition card based on ISA interface, PCI interface, serial and parallel interfaces can no longer meet people's demand for high-resolution, real-time image acquisition. A research based on FPGA and USB3.0 high-speed interface, real-time high-speed image acquisition and transmission has become a new hot spot in the field of high-speed image acquisition research at home and abroad.
Aiming at requirements of high-speed transmission and real-time transmission, FPGA is used as the core control chip and USB3.0 high-speed interface to coordinate the work of the framework to achieve high frame rate, high resolution, real-time high-speed image acquisition and transmission. Upper computer perform is used for visualization operations and data storage. The overall system adopts the hardware design method after the hardware first, and the system modules are tested and verified by simulation. By implementing the image pre-processing operations such as filtering and edge detection in the FPGA, it is verified that the unique parallel data processing method of FPGA has great advantages in signal and image processing.
In the hardware design part of the system, the OV5640 sensor is used as the acquisition front-end. Altera's Cyclone IV E series FPGA is selected as the system control chip, and the DDR2 memory chip is used for data buffering. Cypress's USB3.0 integrated USB 3.0 chip is used as the data speed interface. This part completes the circuit design of each module and the physical production of the acquisition card PCB. System software design is mainly divided into FPGA logic program part, USB3.0 firmware program part and upper computer application software part. By configuring a "soft core" on the FPGA, the Qsys system completes the configuration and initialization of the OV5640. The data path between FPGA and FX3 is completed by the GPIF II interface. Write the state machin
e to complete the Slave FIFO timing control, complete the USB3.0 firmware program design and development in Eclipse. The upper computer adopts VS2013 software to design by MFC, so as to complete the overall image acquisition data path and display and save in the upper computer.
The overall design achieves the expected requirements, each module function is normal, the USB3.0 transmission speed is stable at 320MB/s, and the image resolution
saved by the host computer to the PC hard disk is 1920*1080, which is consistent with the sensor register settings, and the acquisition card image acquisition. The frame rate is 30fps, and the filtering and edge detection pre-processing meets the requirements. The acquisition system has practical application value and research significance.
KEYWORDS:FPGA; USB3.0; High-Speed Transmission; Image Processing; SOPC
目录
rct-341
第一章绪论 (1)
气胀式救生衣1.1 研究的背景与研究意义 (1)
1.2 研究现状以及趋势 (2)
1.3 课题来源及论文研究的主要内容 (5)
1.4 论文组织结构安排 (6)
第二章采集系统硬件设计与实现 (7)
2.1采集系统设计需求 (7)
2.2系统硬件设计方案 (7)
2.2.1 USB3.0传输方案的讨论 (7)
2.2.2 系统模块组成 (8)
2.2.3系统整体框架 (9)
2.3 FPGA逻辑电路设计 (9)
2.3.1 FPGA技术概述 (9)
2.3.2 外设与IO BANK分组 (10)
2.3.3 FPGA供电电路设计 (11)
2.3.4 FPGA时钟电路设计 (13)
2.3.5 FPGA配置电路设计 (13)
2.4 CMOS图像传感器电路设计 (15)
2.4.1 CMOS OV 5640图像传感器 (15)
2.4.2 OV 5640与FPGA硬件电路连接 (16)
2.5 DDR2 SDRAM硬件电路设计 (17)
2.5.1 DDR2芯片介绍 (17)
2.5.2 DDR2与FPGA连接 (19)
2.5.3 DDR2供电设计 (21)
2.6 USB3.0电路设计 (23)
密封性测试2.6.1 USB3.0技术概述 (23)
2.6.2 CYUSB3014简介 (24)
2.6.3 USB3.0供电设计 (25)
2.6.4时钟与复位电路设计 (27)
2.6.5 USB3.0配置电路设计 (28)
2.6.6 CYUSB3014芯片接口电路 (30)
2.7 采集系统PCB设计 (31)
2.7.1 PCB分层设计 (31)
2.7.2 PCB布局设计 (32)
2.7.3 PCB布线设计 (32)
2.8本章小结 (33)
环保万能胶
第三章采集系统软件设计 (34)
3.1 CMOS图像传感器程序设计 (34)
3.1.1基于FPGA的SOPC技术 (34)
3.1.2 Qsys系统开发流程 (36)
3.1.3图像传感器软件设计 (37)
3.2 数据重组模块程序设计 (41)
3.3 DDR2控制器程序设计 (42)
3.3.1 Cyclone IV E系列FPGA双数据速率实现方式 (42)
3.3.2 DDR2 SDRAM典型传输时序 (43)
3.3.3 DDR2 IP核生成及仿真 (44)
3.3.4 DDR2读写数据逻辑控制 (46)
3.4 USB3.0程序设计 (48)
3.4.1 USB3.0的控制逻辑程序设计 (48)
3.4.2 USB3.0芯片固件程序设计 (54)
3.5 上位机应用软件设计 (57)
3.6 本章小结 (58)
第四章图像预处理及系统联调测试 (60)
4.1基于FPGA的图像预处理算法概述 (60)
4.2均值滤波算法的FPGA实现 (61)
4.2.1均值滤波算法简介 (61)
4.2.2均值滤波算法实现 (61)
4.3边缘检测算法的FPGA实现 (65)
拼接处理器4.3.1边缘检测算法简介 (65)
4.3.2边缘检测算法实现 (67)
4.4图像采集系统联调测试 (68)
4.4.1采集系统硬件测试 (68)
4.4.2数据传输带宽测试 (68)
4.4.3上位机软件测试 (70)
4.4.4系统联调测试 (71)
4.5本章小结 (72)
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