module Memorys(DataIn,WrEn,Adr,DataOut,clk,Run);
input [31:0]DataIn;果壳箱
input [4:0]Adr;
input WrEn,clk,Run;
output [31:0]DataOut;
reg [31:0] DataOut;
reg [31:0]data[31:0];
integer count;
always @(posedge clk)
begin
if(WrEn==1'b1 && Run==1'b1)
begin
data[Adr]=DataIn;
DataOut=DataOut;
end
if(Run==1'b1)
DataOut=data[Adr];
氚电池 if(Run==1'b0)
for(count=0;count < 32;count=count+1)
data[count]=8'h00A62F02 * count;
end、
endmodule
仿真图
module Registers(Ra,busA,Rb,busB,Rw,busW,clk,RegWr,Run);
input [4:0] Ra,Rb,Rw;
input clk,RegWr,Run;
input [31:0]busW;
output [31:0] busA,busB;
reg [31:0]data[31:0];pst168
integer count;
assign busA=data[Ra];
assign busB=data[Rb];
always @(posedge clk)
begin
if(RegWr==1'b1 && Run==1'b1)
data[Rw]=busW;
if(Run==1'b0)
begin
for(count=0;count <32;count=count+1)
begin
data[count]=8'h020CDA45 * count;
end
end
end
endmodule
、环模
仿真图
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