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Abstract This application note describes how to build a Spartan™-3E embedded system that is used to
determine the optimal phase shift of a DDR (Double Data Rate) memory feedback clock. In this
system, the DDR memory is controlled by a controller that is attached to the OPB (On-chip
气调门Peripheral Bus) and is used in an embedded microprocessor application. This reference
system also uses a Digital Clock Manager (DCM) that is configured so that the phase of its
output clock can be changed while the system is running. A GPIO (General Purpose
Input/Output) core together with a custom control logic core and the included software
application dynamically control the phase shift. The GPIO output is controlled by a software
application that runs on a MicroBlaze™ microprocessor, while this application runs out of an
internal FPGA BRAM. The application starts with an initial phase shift value, then decrements
and increments to find the entire passing phase shift range. At each phase shift value, the
application performs memory tests, then records if the tests have passed or failed. The passing
range and optimal phase shift value for the given system board are reported by printing them to
a HyperT erminal through a UART . The optimal phase shift value is calculated by choosing the center of the passing range.
Included
Systems Included with this application note is one reference system (s3e1600e_mb_dcm_phase_shift)
built for the Xilinx Spartan-3E 1600E Edition Development board. The reference system is available for downloading at:
/bvdocs/appnotes/xapp977.zip Introduction When building a new circuit board that uses an FPGA and a DDR memory, the optimal phase
shift for the DDR feedback clock must be determined, because double data rate memory
controllers write and read data at both the rising and falling edges of the controller clock. The
optimal time to sample the data is at the midpoint of each of the half clock cycles, or at 90 and
270 degrees as shown in Figure 1. To ensure that the sampling of the read data occurs at these
desired times, it is necessary to account for the routing delay of the DDR feedback clock and
adjust the clocks to the DDR input data registers appropriately. In a Xilinx FPGA system this
智慧交通沙盘can be simply accomplished with the help of a DCM. The DCMs that are available in most Xilinx FPGAs have a built in phase shifter component. If the DDR feedback clock is fed into a DCM,
the phase of the output clocks can be adjusted so that the 90 and 270 degree shifted clocks rise
at the midpoint of the controller clock half periods. The only difficult part with this approach is
knowing exactly how much to shift the phase. This amount is dependent not only on how much
routing delay there is from the DDR chip to the FPGA, but also on how much delay there is from
the FPGA input pin to the DCM. This application note explains how to create a simple system
to experimentally find this optimal phase shift without having to know anything about the routing
delays.
Application Note: Embedded Processing
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Hardware and Software Requirements The hardware and software requirements are:•Xilinx Spartan-3E 1600E Edition development board •Xilinx Platform USB programming cable
•RS232 null-modem serial cable
•Serial Communications Utility Program (e.g. HyperTerminal)•Xilinx Platform Studio 9.1.01i
•Xilinx Integrated Software Environment (ISE™) 9.1.03i
Reference System Specifics The included reference system targets the Spartan-3E 1600E Edition development board. The system uses the MicroBlaze embedded processor. As shown in the system block diagram in Figure2, the system also includes the MCH (Multi-Channel) OPB DDR (Dual Data Rate) memory controller, the OPB GPIO IP core, the OPB UART Lite IP core, and a DCM Phase Shift custom logic core.
The address map for this reference system is shown in Table1.
DDR Data Capture
Figure 2:
Reference System Block Diagram
Address Map
The bitstream for this system, download.bit , is available in the ready_for_download/ directory under the project root directory.
Although the supplied reference system is specifically targeted to work on the Spartan-3E 1600E Edition development board, it can be modified to work on any other board that contains an FPGA and a DDR memory chip. Due to slightly different functionality of the DCMs from other architectures, it is necessary to review the DCM section of the data sheet for the architecture being targeted and the appropriate modifications made. This application note describes how to go through the process of building a Spartan-3E system through the Base System Builder (BSB), that is available through the Embedded Development Kit (EDK), then modifying that system to find the optimal phase shift for the DDR feedback clock.
Building the Initial System Through BSB
1.Start the BSB wizard to create a new EDK project.
2.Either choose one of the boards supported by BSB or create a project for a custom board.
Choose the FPGA that is available on the board and define whether the system will use a PowerPC™ or a MicroBlaze soft processor (the reference system that accompanies this application note provides examples with a MicroBlaze).
3.Choose the frequencies for the reference, processor, and bus clocks (for example, the
supplied Spartan-3E reference system has the reference, processor, and OPB clocks set to 66.67 MHz and the DDR clock set to 133.33 MHz). If 66.67 MHz is chosen for the reference frequency, then the DDR clock will be set to 133.33 MHz.
Note:The methodology used here for determining the optimum phase shift value is dependent on the clock period of the DDR, so any variation in DDR clock period will require recalculation of the VARIABLE phase shift steps and MIN and MAX valid phase shift range. This is explained in more detail in a later section.
4.Although no debug module is needed for this system, it can be added if desired.
5.Add a BRAM block on OPB or PLB or LMB. The supplied reference systems uses 16KB of
BRAM on the LMB.
Note:The reason why it is imperative that this application is run out of local BRAM is that at certain phase shifts the data reads from the DDR memory will fail. If the application resided in DDR memory, the microprocessor would not be able to fetch instructions and the application would hang.
6.The other peripherals that are needed to run this application are a DDR memory controller,
a UART, and a GPIO core.
a.Set up the DDR controller parameters so that they correspond to the parameters of the
DDR chip.
Table 1: Reference System Address Map Peripheral
Instance Version Base Address High Address opb_mdm
debug_module 2.00.a 0x414000000x4140FFFF lmb_bram_if_cntlr
dlmb_cntlr 1.00b 0x000000000x00001FFF lmb_bram_if_cntlr
ilmb_cntlr 1.00.b 0x000000000x00001FFF opb_uartlite
RS232_DTE 1.00.b 0x406000000x4060FFFF mch_opb_ddr
DDR_SDRAM_32Mx16 1.00.c 0x220000000x23FFFFFF opb_gpio opb_gpio_0 3.01.b 0x400000000x4000FFFF
b.This reference system uses a UART Lite attached to the OPB. The sole purpose of the
UART is to communicate the optimal phase shift value and passing range to the user through a HyperTerminal.
c.The GPIO core is used to control and determine the status of the DCM phase shift logic
via the software application.
Note:More details for setting up the parameters and ports for each core will be provided in the next s
ection.
7.Additional peripherals can also be added to the system, but are not necessary to run the
phase shifting application.
8.Direct STDIN and STDOUT to the UART receive and transmit ports.
9.Select the Memory test option to have Base System Builder create a sample application
and a linker script.
10.Make sure that the instructions, data and the stack for the application program are all
contained within the processor local memory block or BRAM.
11.Review the summary of the system created and select Generate.
12.The initial base system has been created and can be modified to run the application that
determines the optimal phase shift for the DDR memory feedback clock.
Note:If the system was created for a custom board, be sure to edit the system constraints file,
data/system.ucf, to lock down the UART and DDR pins. Additionally, the correct position number of the FPGA in the JTAG chain in d (default is 1) may have to be set.
Although not necessary, it is a good idea to build this initial system and run the sample Memory application built by BSB to make sure that the system is set up correctly and all the location constraints are what they should be.
Modifications Required to the Initial System
The initial build does not have to be identical to the one described in the previous section, however it must have a processor, local memory, a DDR controller, a UART, and a GPIO core. This section describes what is needed to modify a BSB generated Spartan-3E system. It describes what must be modified to add in the logic, cores, parameters, and connections needed for the optimum phase shift application and that are not selectable through the BSB. It involves changing the clocking so that the phase shifting of the DCM, which is fed by the DDR feedback clock, is variable and connects the DCM phase shifting control inputs/outputs of the DCM to the ports of the GPIO core and the custom phase shift logic core. The next section will detail how to change the sample application so that it per
陶瓷纤维管forms the phase shifting by controlling the outputs of the GPIO.
Note:Because of the high fanout for OPB_Rst, the BSB-generated system may fail timing for some of the reset paths. It is recommended to use the Processor System Reset Module because this helps with fanout of the resets to the buses and the peripheral cores. The included reference design uses the Processor System Reset Module core to provide a more robust reset strategy. This core is available in the EDK tools in the IP Catalog Library under Reset Control. The inclusion of this core is not described in this document but the user can refer to the included reference design for example port connections and parameter settings for this core.
How to Modify the Clocking Structure and Other Related Hardware
There is a custom core included in the design project that has logic for controlling the DCM Phase Shifter which must be incorporated into the design. Also, there is miscellaneous utility logic that must be added to connect signals from the GPIO to the DCMs.
Adding the Custom Phase Shifter Control Logic Core to the Design
1.To modify the clocking structure, copy the entire DCM Phase Shift Logic core,
防水防漏电插座
dcm_phase_shift_logic_v1_00_a, from the <project>/pcores/ area of the included reference system to the <project>/pcores/ area of the user project.
2.In the IP Catalog tab of the Project Information Area window under the Project Repository
Section, add the dcm_phase_shift_logic core by right clicking and selecting the Add IP option as shown in Figure 3. If dcm_phase_shift_logic does not appear in the list of available cores, XPS must be re-synced by selecting Project -> Re-scan User
Repository .
Adding the Utility Logic to the Design
1.The utility logic that is needed consists of an AND function, which is added when using the
Utility Reduced Logic core, and an INVERTER using a Utility Vector Logic core.
2.Go to the IP Catalog tab of the Project Information Area window under the Utility Section
and add the util_reduced_logic
core by right clicking and selecting the Add IP option. Add in the util_vector_logic in the same way as shown in Figure 4.
Connecting the Modules for Dynamic Phase Shifting The diagram in Figure 5 illustrates how the connections are made between the various
modules to control the DCM phase shifter. This configuration is representative of the supplied
Figure 3: Adding the DCM Phase Shift Logic Core to the Design
Figure 4: Adding the Utility Logic Cores to the Design
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