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Summary
The SRL16 is an alternative mode for the look-up tables where they are used as 16-bit shift registers. Using this Shift Register LUT (SRL) mode can improve performance and rapidly lead to cost savings of an order of magnitude. Although the SRL16 can be automatically inferred by the software tools, considering their effective use can lead to more cost-effective designs.This application note applies to all Spartan™-3 Generation FPGA families, which include the Spartan-3 family, the Spartan-3L family, and the Spartan-3E family.
Introduction
Spartan-3 Generation FPGAs can configure the look-up table (LUT) in a SLICEM slice as a 16-bit shift register without using the flip-flops available in each slice. Shift-in operations are synchronous with the clock, and output length is dynamically selectable. A separate dedicated output allows the cascading of
any number of 16-bit shift registers to create whatever size shift register is needed. Each CLB resource can be configured using four of the eight LUTs as a 64-bit shift register.
This document provides generic VHDL and Verilog submodules and reference code examples for implementing from 16-bit up to 64-bit shift registers. These submodules are built from 16-bit shift-register primitives and from dedicated MUXF5, MUXF6, and MUXF7 multiplexers.These shift registers enable the development of efficient designs for applications that require delay or latency compensation. Shift registers are also useful in synchronous FIFO and
Content-Addressable Memory (CAM) designs. To quickly generate a Spartan-3 shift register without using flip-flops (i.e., using the SRL16 element(s)), use the CORE Generator™ RAM-based Shift Register module.
Shift Register Architecture
The structure of the SRL16 is described from the bottom up, starting with the shift register and then building up to the surrounding FPGA structure.
LUT Structure
The Look-Up Table can be described as a 16:1 multiplexer with the four inputs serving as binary select lines, and the values programmed into the Look-Up Table serving as the data being selected (see Figure 1).
除湿机回收With the SRL16 configuration, the fixed LUT values are configured instead as an addressable shift register (see Figure 2). The shift register inputs are the same as those for the synchronous RAM configuration of the LUT: a data input, clock, and clock enable (not shown). A special
Application Note: Spartan-3 FPGA Series
Figure 1: LUT Modeled as a 16:1 Multiplexer
output for the shift register is provided from the last flip-flop, called Q15 on the library primitives or MC15 in the FPGA Editor. The LUT inputs asynchronously (or dynamically) select one of the 16 storage elements in the shift register.
Figure 2: LUT Configured as an Addressable Shift Register
Dynamic Length Adjustment
The address can be thought of as dynamically changing the length of the shift register. If D is used as the shift register output instead of Q15, setting the address to 7 (0111) selects Q7 as the output, emulating an 8-bit shift register. Note that since the address lines control the mux, they provide an asynchronous path to the output.
Logic Cell Structure
Each SRL16 LUT has an associated flip-flop that makes up the overall logic cell. The addressable bit of the shift register can be stored in the flip-flop for a synchronous output or can be fed directly to a combinatorial output of the CLB. When using the register, it is best to have fixed address lines selecting a static shift register length to avoid timing hazards. Since the clock-to-output delay of the flip-flop is faster than the shift register, performance can be improved by addressing the second-to-last bit and then using the flip-flop as the last stage of the shift register. Using the flip-flop also allows for asynchronous or synchronous set or reset of the output.
The shift register input can come from a dedicated SHIFTIN signal, and the Q15/MC15 signal from the last stage of the shift register can drive a SHIFTOUT output. The addressable D output is available in all SRL primitives, while the Q15/MC15 signal that can drive SHIFTOUT is only available in the cascadable SRLC16 primitive.
Figure 3: Logic Cell SRL Structure
The SRL16 can shift from either LSB to MSB or MSB to LSB according to the application. Although the device arbitrarily names the output MC15, it can be the LSB of the user function.
Slice Structure
The two logic cells within a slice are connected via the SHIFTOUT and SHIFTIN signals for cascadin
g a shift register up to 32 bits (see Figure 4). These connect the Q15/MC15 of the first shift register to the DI (or Q0 flip-flop) of the second shift register.
If dynamic addressing (or "dynamic length adjustment") is desired, the two separate data outputs from each SRL16 must be multiplexed together. One of the two SRL16 bits can be selected by using the F5MUX to make the selection (see Figure 5).
CLB Structure
The Spartan-3 Generation CLB contains four slices, each with two Look-Up Tables, but only two allow LUTs to be used as SRL16 components or distributed RAM. The two left-hand
SLICEM components allow their two LUTs to be configured as a 16-bit shift register. The same cascading of SHIFTOUT to SHIFTIN available between the LUTs in the SLICEM is also
available to connect the two SLICEM components. The four left-hand LUTs of a single CLB can be combined to produce delays up to 64 clock cycles (see Figure 6).
Figure 4:
Shift Register Connections Between Logic Cells in a Slice
Figure 5: Using F5MUX for Addressing Multiple SRL16 Components
Figure 6: Cascading Shift Register LUTs in a CLB
The multiplexers can be used to address multiple SLICEMs similar to the description for combining the two LUTs within a SLICEM. The F6MUX can be used to select from three or four SRL16 components in a CLB, providing up to 64 bits of addressable shift register (see Figure7).
Figure 7: Using F6MUX to Address a 64-Bit Shift Register
Library Primitives
and cascadable output (Q15) combinations.
Table 1 lists all of the available primitives for synthesis and simulation.Initialization in VHDL and Verilog Code
A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the INIT attribute is attached to the 16-bit shift register instantiation and is copied in the EDIF output file to be compiled by Xilinx Alliance Series tools. The VHDL code simulation uses a generic parameter to pass the attributes. The Verilog code simulation uses a defparam parameter to pass the attributes.
The S3_SRL16E shift register instantiation code examples (in VHDL and Verilog) illustrate these techniques (see “VHDL and Verilog Templates,” page 12). S3_SRL16E.vhd and .v files are not a part of the documentation.
Port Signals
Clock — CLK
Either the rising edge or the falling edge of the clock is used for the synchronous shift-in. The data and clock enable input pins have set-up times referenced to the chosen edge of CLK.Data In — D
tmchThe data input provides new data (one bit) to be shifted into the shift register.
Table 1: Shift Register Primitives
Primitive Length Control Address Inputs Output SRL1616 bits CLK A3, A2, A1, A0Q SRL16E 16 bits CLK, CE A3, A2, A1, A0Q SRL16_116 bits
CLK A3, A2, A1, A0Q SRL16E_116 bits CLK, CE A3, A2, A1, A0Q SRLC1616 bits CLK A3, A2, A1, A0Q, Q15SRLC16E 16 bits CLK, CE A3, A2, A1, A0Q, Q15SRLC16_116 bits CLK A3, A2, A1, A0Q, Q15SRLC16E_1
16 bits
CLK, CE
A3, A2, A1, A0
Q, Q15
Figure 8: SRLC16E Primitive
Clock Enable — CE (optional)
The clock enable pin affects shift functionality. An inactive clock enable pin does not shift data into the shift register and does not write new data. Activating the clock enable allows the data in (D) to be written to the first location and all data to be shifted by one location. When available, new data appears on output pins (Q) and the cascadable output pin (Q15).
防水伸缩缝
Address — A3, A2, A1, A0
Address inputs select the bit (range 0 to 15) to be read. The n th bit is available on the output pin (Q). Address inputs have no effect on the cascadable output pin (Q15), which is always the last bit of the shift register (bit 15).破碎机刀具
Data Out — Q
The data output Q provides the data value (1 bit) selected by the address inputs.
Data Out — Q15 (optional)
The data output Q15 provides the last bit value of the 16-bit shift register. New data becomes available after each shift-in operation.
Inverting Control Pins
The two control pins (CLK, CE) have an individual inversion option. The default is the rising clock edge and active High clock enable.
GSR
The global set/reset (GSR) signal has no impact on shift registers.
Attributes
Content Initialization — INIT离心制丸机 The INIT attribute defines the initial shift register contents. The INIT attribute is a hex-encoded bit vector with four digits (0000). The left-most hexadecimal digit is the most significant bit. By default the shift register is initialized with all zeros during the device configuration sequence, but any other configuration value can be specified.
Location Constraints
Figure9 shows how the slices are arranged within a CLB. Each CLB has four slices, but only the two at the bottom-left of the CLB can be used as shift registers. These are both designated SLICEM in C
LB positions S0 and S1. The relative position coordinates are X0Y0 and X0Y1. To constrain placement, these coordinates can be used in a LOC property attached to the SRL primitive. Note that the dedicated CLB shift chain runs from the top to the bottom, but the start and end of the shift register can be in any of the four SLICEM LUTs.
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