A new valley-detection method for the quasi-resonance switching

A New Valley-Detection Method for the Quasi-Resonance Switching

Gwan-Bon Koo, Sang-Cheol Moon, and Jin-Tae Kim

Korea Power Conversion, Fairchild Semiconductor

82-3, Dodang-dong, Wonmi-gu, Bucheon-si, Gyeonggi-do, KOREA

Abstract-To reduce switching losses in flyback topologies with a

single switch, many kinds of quasi-resonant techniques are used.

One of them is a valley-switching method which finds valleys of

the drain-to-source voltage of the switch and makes the next

switching begin at one of the valleys. It results in high efficiency

and low EMI but an additional pin is required to detect where

valleys are in view point of a control IC. This paper suggests a

new valley-detection method without increasing the number of

pin. Operational principles and experimental results will be

shown to verify the validity of the proposed method.

I. INTRODUCTION

Flyback is one of the most popular topologies in medium

and low power applications due to its simplicity. It can

implement isolated switching mode power supplies (SMPS)

with one switching component and one transformer resulting

in low manufacturing cost. However, the switching losses are

unavoidable in hard-switching mode as can be seen in Fig. 1.

VoVdcVstrD+vds_id

When it operates in discontinuous conduction mode (DCM)

with a fixed frequency, the drain-to-source voltage of the

MOSFET is arbitrary. So the capacitive loss of the MOSFET

during switch turn-on transition cannot be predicted and

minimized. Therefore many kinds of quasi-resonant

techniques are used to increase total efficiency by reducing

switching losses in flyback topologies [1~2]. A valley-switching technique is one of them [3~4]. When the flyback

topologies operate in DCM, the drain-to-source voltage of the

switch resonates after the current of the secondary rectifying

diode runs dry. In a valley-switching technique, the switching

component always turns on at the instant of the first

minimum value of the drain-to-source voltage of the switch

even though the input voltage and load current are changed

[3]. It allows good EMI (Electromagnetic Interference) and

thermal performance, as well as high efficiency. Its operating

waveforms are shown in Fig. 2.

However, it requires an additional pin and a couple of

external components such as resistors and capacitors to detect

where the valleys are. Fig. 3 shows an external circuit to

indirectly detect the second valley via the bias winding

voltage and its key waveforms. The bias winding voltage

reflects the drain-to-source voltage without a dc offset

corresponding to the dc link voltage, as shown in Fig. 3(b).

The shape of the drain-to-source voltage of several hundreds

PWMVfbVccGNDFig. 1. A conventional flyaback converter with its key waveforms

Fig. 2. Drain current and drain-to-source voltage waveforms with

valley-switching operation

978-1-4244-4783-1/10/$25.00 ©2010 IEEE540

VoVdcACINNpVstrDSyncVS-PWMVfbVccGNDNaRaRbAdditionalRcComponentsCaDaas shown in Fig. 3(d). Considering an internal delay time

around 200 ns, adjusting the instant where vSync reaches an

internal low threshold voltage Vthl to the valley of the drain-to-source voltage of the MOSFET is possible [5].

In areas where the keen price competition exists, adding

one more pin and several components to detect valleys only

would be critical for manufacturers to select a control IC.

Therefore it is highly required to change the method to detect

valleys and to combine the “Sync” pin with one of existing

protection pins such as the pin for line-sensing.

Section II introduces the concept of a new valley-detection

method and one embodiment for commercial ICs.

Experimental results to prove the validity of the proposed

method and the conclusion are discussed in Sections III and

IV, respectively.

II.

THE

PROPOSED

METHOD TO

DETECT

VALLEYS

A. Basic Concept

The drain current of the MOSFET increases with a slope of

Vdc/Lm during turn-on period T1 where Vdc is the dc link

voltage and Lm is the magnetizing inductance of the main

transformer. After the MOSFET turns off, the current of the

secondary rectifying diode will decrease with a slope of -Vo/Ls and finally reach to zero during T2 due to a DCM

operation where Vo is the output voltage and Ls is the

secondary side inductance of the main transformer. The

resonance between Lm and Coss begins after the run-dry of

the secondary rectifying diode where Coss is the output

capacitance of the MOSFET. Therefore the first valley comes

after a time of a half of resonance period between Lm and

Coss (T3) goes. In flyback topologies, the magnetizing

current of the main transformer is composed of the drain

current of the MOSFET and the reflected current of the

secondary rectifying diode. Fig. 4 shows the drain-to-source

voltage of the MOSFET and the magnetizing current of the

(a)Vdct(b)tNa/Np(c)< 0.3VInternal delay200nst(d)tFig. 3. External circuit for detecting valleys and key waveforms

volt is observed on the “Sync” pin with scaling down using

the turns ratio Na/Np and the voltage divider Ra, Rb, and Rc,

where Na and Np are the turns numbers of the bias and

primary windings, respectively. Since control IC usually

cannot accept a negative voltage exceeding -0.3 V as an

input, a diode Da is needed to remove negative parts from

Fig. 3(b). That is why a diode Da is added and the voltage

divider is composed of three resistors rather than two

resistors. However, the most important information, i.e.

where valleys are, disappears unfortunately. Now capacitor

Ca has a role. The observed voltage on the “Sync” pin is

delayed by time constant made by Ca and the voltage divider,

Fig. 4. Drain-to-source voltage and magnetizing current of the main

transformer along with the MOSFET gate signal

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main transformer iLm along with the MOSFET gate signal vgs. internal delay time is a constant which is a slightly smaller

The magnetizing inductance is magnetized with the dc link than a half of resonance period between Lm and Coss

voltage and demagnetized with the reflected output voltage. If

generally used. Then the next gate turn-on signal will be

the dc link voltage, reflected output voltage, turn-on time of generated near the first valley by tuning the external resistors

the MOSFET, magnetizing inductance, and output to sense the dc link voltage taking the independent current

capacitance are known, the time duration T1, T2, and T3 are

sink and the internal delay time into account, as shown in Fig.

calculated so that the turn-on instant of the next switching is

6. To meet the next turn-on signal with the first valley, the

slope of the drain current should be determined as the thick

defined easily.

solid line instead of the dotted lines. Once the external

sensing resistors are tuned well at certain dc link voltage, the

B. One Embodiment and Its Operational Principles

Fig. 5 shows one embodiment for the basic concept. There

controller will find the instant of the next gate turn-on around

is an internal capacitor, Cint which will be charged and

the first valley over whole dc link voltage ranges.

The information about the dc link voltage through the

discharged by a current source and a current sink. The current

sink is an independent one representing the reflected output

“Line Sense” pin could be used for other protections such as a

voltage nVo. The current source is dependent on the dc link

brownout function, variable current limit function, and so on.

voltage Vdc. These two current source and sink will charge

The proposed method allows the pin for sensing the dc link

and discharge the internal capacitor by turns according to the

voltage to include the function of finding valleys. It results in

gate signal. After charged by the current source during a turn-saving the manufacturing cost for the control IC, and

on time of the switch, the internal capacitor voltage decreases

reducing external components.

by the current sink during the rest cycle. When the internal

capacitor voltage drops under VTH which is almost zero, the

III. THE

EXPERIMENTAL

RESULTS

comparator outputs high so that the next gate turn-on signal is

To verify the performance of the embodiment described in

produced to the switch with an internal delay time. The

Section II-B, a prototype is constructed and experimented

with discrete components. The specifications of the prototype

are shown in Table I.

TABLE I

SPECIFICATIONS OF THE

PROTOTYPE

Fig. 5. One embodiment for the basic concept

Dc Link Voltage 150 Vdc ~ 310 Vdc

Output Voltage 5 V

Output Load Current 0.5 A ~ 2 A

Cint 2.2 nF

Current Sink 1.94 mA

Internal Delay Time 1.44 us

Resonance Period 2.14 us

VTH 1.6 V

ttFig. 6. How to tune the external sensing resistors up

The internal delay time has to be shorter than a half of the

resonance period to tune the external sensing resistors up

easily. But in the prototype, a longer internal delay time is

required because VTH is not zero. A possible internal

capacitor to be implemented on a chip is several decades of

pico-farad, in general. To make the experiments easy, 2.2 nF

as the internal capacitor is selected in the prototype.

Therefore the internal current sink increases as well. For the

case of manufacturing a control IC, several decades of pico-farad and several decades of micro-ampere will be used as the

internal capacitor and current sink, respectively.

Figs. 7 and 8 show the valley switching well-matched at

different dc link voltages. Figs. 7 and 8 are measured under

full load condition with 150 Vdc and 310 Vdc of link voltage,

respectively. They are well agreed with the theoretical

analysis.

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Fig. 7. Key waveforms at full load with 150 Vdc

Fig. 8. Key waveforms at full load with 310 Vdc

Fig. 9. Key waveforms at full load with 200 Vdc

Fig. 10. Key waveforms at 25% load current of the rated condition

with 200 Vdc

Figs. 9 and 10 show the case of load current change. Fig. 9

is measured at full load condition with 200 Vdc of link

voltage. The case of 25% load of the rated condition with 200

Vdc is shown in Fig. 10. It is verified that the proposed

method to detect valleys works well even though the dc link

voltage and load current change.

IV. CONCLUSIONS

A new valley-detection method was introduced in this

paper. Instead of the existing method to indirectly detect

valleys through a bias winding with a couple of external

components, a method to detect the dc link voltage was

suggested. It results in combining the pin which is connected

to the bias winding for detecting valleys with a line sense pin

so that one pin could be saved.

A prototype of 10 W was constructed and experimented to

prove the validity of the proposed method. The test results

were well agreed with the theoretical analysis. Finding the

first valley and turning the next switching on worked well

even if the dc link voltage and load current change.

A new control IC for a quasi-resonance switching could be

made using the proposed method without increasing the

number of pins. It will allow for the IC users to reduce the

total bill of materials (BOM.)

REFERENCES

[1] K. H. Liu and F. C. Lee, “Resonant switches – a unified approach to

improved performances of switching converters,” in Proceedings of the

International Telecommunications Energy Conference, 1984, pp. 344-351.

[2] D. Balocco and C. Zardini, “The half-wave quasi-resonant ZCS flyback

converter as an automatic power factor preregulator: An evaluation,” in

IEEE Applied Power Electronics Conference, 1996, pp. 138-144.

[3] FSCQ-series, Green Mode Fairchild Power Switch (FPSTM) datasheet,

Fairchild Semiconductor.

[4] “Design Guidelines for Flyback Converters using FSQ-series Fairchild

Power Switch (FPSTM),” Literature No. AN-4150, Fairchild

Semiconductor.

[5] FSQ510, Green Mode Fairchild Power Switch (FPSTM) datasheet,

Fairchild Semiconductor.

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