Alliance Semiconductor AS7C4098 AS7C34098 数据手册

查询AS7C34098-10供应商January 2005®AS7C4098AS7C340985V/3.3V 256K × 16 CMOS SRAMFeatures•AS7C4098 (5V version)•AS7C34098 (3.3V version)•Industrial and commercial temperature•Organization: 262,144 words × 16 bits•Center power and ground pins•High speed-10/12/15/20 ns address access time-5/6/7/8 ns output enable access time•Low power consumption: STANDBY-110 mW (AS7C4098)/max CMOS-72 mW (AS7C34098)/max CMOS•Individual byte read/write controls•Easy memory expansion with CE, OE inputs•TTL- and CMOS-compatible, three-state I/O•44-pin JEDEC standard packages-400-mil SOJ-TSOP 2•Low power consumption: ACTIVE-1375 mW (AS7C4098)/max @ 12 ns-576 mW (AS7C34098)/max @ 10 ns•ESD protection ≥ 2000 volts•Latch-up current ≥ 100 mALogic block diagramA0A1A2A3A4A6A7A8A12A13I/O1–I/O8I/O9–I/O16WEVCC1024 × 256 × 16Array(4,194,304)GNDPin arrangement for SOJ and TSOP 244-pin (400 mil) SOJ TSOP2A0A1A2A3A4CEI/O1I/O2I/O3I/O4VCCGNDI/O5I/O6I/O7I/O8WEA5A6A7A8A9332313423A17A16A15OEUBLBI/O16I/O15I/O14I/O13GNDVCCI/O12I/O11I/O10I/O9NCA14A13A12A11A10I/O

bufferRow

DecoderControl circuitColumn decoderA5A9A10A11A14A15A16A17UBOELBCESelection guide–10Maximum address access timeMaximum output enable access timeMaximum operating currentMaximum CMOS standby currentAS7C4098AS7C34098AS7C4098AS7C34098105–160–20–2020–2020–220UnitnsnsmAmAmAmA1/13/05; v.1.9Alliance SemiconductorP. 1 of 10Copyright © Alliance Semiconductor. All rights reserved.

AS7C4098AS7C34098®Functional descriptionThe AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devicesorganized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, andsimple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns areideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bankmemory systems.

When CE is High the device enters standby mode. The standard AS7C4098/AS7C34098 is guaranteed not to exceed 110/72mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chipenable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). Toavoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) orwrite enable (WE).A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chipdrives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, orwrite enable is active, output drivers stay in high-impedance devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes tobe written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.

All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V(AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ and TSOP 2 te maximum ratingsParameterVoltage on VCC relative to GNDVoltage on any pin relative to GNDPower dissipationStorage temperature

Ambient temperature with VCC appliedDC current into outputs (low)DeviceAS7C4098AS7C34098SymbolVt1Vt1Vt2PDTstgTbiasIOUTMin–0.50–0.50–0.50––65–Max+7.0+5.0VCC +0.501.5+150±20UnitVVVW°C°CmA–55 +125Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only andfunctional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not re to absolute maximum rating conditions for extended periods may affect tableCEHLLLWEXHXHOEXHXLLBXXHLHLLUBXXHHLLHLLI/O1–I/O8 HighZHigh ZDOUT HighZDOUTDIN HighZDINI/O9–I/O16 HighZHigh ZHigh ZDOUTDOUTHigh ZDINDINMode Standby(ISB, ISB1)Output disable (ICC)Read (ICC)LLXHLWrite (ICC)Key: X = Don’t care, L = Low, H = High.1/13/05; v.1.9Alliance SemiconductorP. 2 of 10

AS7C4098AS7C34098®Recommended operating conditionsParameterAS7C4098Supply voltageAS7C34098AS7C34098AS7C4098Input voltagecommercialindustrialAS7C34098SymbolVCC

(12/15/20)VCC (10)VCC

(12/15/20)VIHVIHVIL1Ambient operating temperatureTATAMinTypical4.53.153.02.22.0–0.50–405.03.33.3–––––Max5.53.63.6VCC + 0.5VCC + 0.50.87085UnitVVVVVV°C°C1 VIL min = –1.0V for pulse width less than operating characteristics (over the operating range)1–10ParameterInput leakage

currentOutput leakage

currentOperating

power supply

currentSymbol|ILI|Test conditionsVCC = MaxVIN = GND to VCCVCC = MaxCE = VIH or OE = VIH

or WE = VIL

VI/O = GND to VCCVCC = MaxMin cycle, 100% dutyCE = VIL, IOUT = 0mAVCC = MaxCE = VIH, f = MaxAS7C4098/AS7C34098AS7C4098/AS7C34098AS7C4098AS7C34098AS7C4098AS7C34098–12–15–20MinMaxMinMaxMinMaxMinMaxUnit–1–1–1–1µA|ILO|––––––––1–160–60–200.4–––––––––2.41250.4–––––––––2.41220.4–––––––––2.41µA180mA100mA606020200.4–mAmAmAmAVVICCISBStandby power

supply currentISB1VOLVOHVCC = MaxAS7C4098CE ≥ VCC – 0.2V, VIN ≥ VCC

– 0.2V or VIN ≤ 0.2V, f = 0AS7C34098IOL = 8 mA, VCC = MinIOH = –4 mA, VCC = MinAS7C4098/Output voltageAS7C340982.4

Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2

ParameterInput capacitanceI/O capacitanceSymbolCINCI/OSignalsA, CE, WE, OE, UB, LBI/OTest conditionsVIN = 0VVIN = VOUT = 0VMax68UnitpFpF1/13/05; v.1.9Alliance SemiconductorP. 3 of 10

AS7C4098AS7C34098®Read cycle (over the operating range)3,9–10ParameterRead cycle timeAddress access timeChip enable (CE) access timeOutput enable (OE) access timeOutput hold from address changeCE Low to output in low ZCE High to output in higfch ZOE Low to output in low ZOE High to output in high ZLB, UB access timeLB, UB Low to output in low ZLB, UB High to output in high ZPower up timePower down timeSymboltRCtAAtACEtOEtOHtCLZtCHZtOLZtOHZtBAtBLZtBHZtPUtPDMin10–––30–0––0–0–Max–10105––5–55–5–1012–––33–0––0–0––12MinMax–12126––6–66–6–1215–––30–0––0–0––15MinMax–15157––7–77–7–1520–––30–0––0–0––20MinMax–20208––9–98–9–20UnitNotesnsnsnsnsns5ns 4,5ns 4,5ns 4,5ns 4,5nsnsnsnsns55Key to switching waveformsRising inputFalling inputUndefined/don’t careRead waveform 1 (address controlled)6,7,9tRCAddresstOHDataOUTPrevious data validtAAData validtOH1/13/05; v.1.9Alliance SemiconductorP. 4 of 10

AS7C4098AS7C34098®Read waveform 2 (CE, OE, UB, LB controlled)6,8,9tRCAddresstAAOEtOLZCEtACEtLZLB, UBtBLZDataOUTtBAData validtBHZtCHZtOEtOHZtOHWrite cycle (over the operating range)11–10ParameterWrite cycle timeChip enable (CE) to write endAddress setup to write endAddress setup timeWrite pulse width (OE = High)Write pulse width (OE = Low)

Write recovery timeAddress hold from end of writeData valid to write endData hold timeWrite enable to output in High-ZOutput active from write endByte enable Low to write endSymbolMintWCtCWtAWtAStWP1tWP2tWRtAHtDWtDHtWZtOWtBW137Max––––––––––5––1288–6–––12MinMax––––––––Min1510310–15Max––––––––––7––Min2900312–20Max––––––––––9––Unitnsnsnsnsnsnsnsnsnsns 4,5ns 4,5ns 4,5ns 4,5Note1/13/05; v.1.9Alliance SemiconductorP. 5 of 10

AS7C4098AS7C34098®Write waveform 1(WE controlled)10,11

tWCtAHtWRAddresstCWCEtBWLB, UBtASWEtDWDataINDataOUTData undefinedtWZtDHData validtOWHigh ZtAWtWPWrite waveform 2 (CE controlled)10,11

tWCAddresstASCEtCWtAWtBWLB, UBtWPWEtDWDataINDataOUTtCLZHigh ZtWZData undefinedData validtOWHigh ZtDHtAHtWR1/13/05; v.1.9Alliance SemiconductorP. 6 of 10

AS7C4098AS7C34098®Write waveform 3

10,11tWCtAHtWRAddresstASCEtAWtBWLB, UBWEDataINDataOUTHigh ZtWZData undefinedtWPtDWData validtDHHigh ZtCWAC test conditions----Output load: see Figure B or Figure pulse level: GND to 3.0V. See Figure rise and fall times: 2 ns. See Figure and output timing reference levels: 1.5V.+3.0VGND90%10%2 nsFigure A: Input pulse90%10%Thevenin equivalent:DOUT+5VDOUT255Ω480ΩC13168Ω+1.728V (5V and 3.3V)+3.3V320ΩC13DOUT350ΩGNDFigure B: 5V Output loadGNDFigure C: 3.3V Output load

Notes111213During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB parameter is sampled, but not 100% test conditions, see AC Test Conditions, Figures A, B, and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state parameter is guaranteed, but not is High for read and OE are Low for read s valid prior to or coincident with CE transition read cycle timings are referenced from the last valid address to the first transitioning or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

All write cycle timings are referenced from the last valid address to the first transitioning applicable.C = 30pF, except on High Z and Low Z parameters, where C = 5pF.1/13/05; v.1.9Alliance SemiconductorP. 7 of 10

AS7C4098AS7C34098®Typical DC and AC characteristics12

1.41.2Normalized

ICC,

ISB1.00.80.60.40.20.0MINNOMINALSupply voltage (V)MAXISBNormalized

ICC,

ISBICCNormalized supply current ICC, ISBvs. supply voltage VCC1.41.21.00.80.60.40.20.0–55–103580125Ambient temperature (°C)Normalized access time tAAvs. ambient temperature TaISBNormalized supply current ICC, ISBvs. ambient temperature TaNormalized

ISB1

(log

scale)62525510.20.04–55–103580125Ambient temperature (°C)Normalized supply current ISB1

vs. ambient temperature TaICCVCC = VCC(NOMINAL)1.5Normalized

access

time1.41.31.21.11.00.90.8MINNormalized access time tAAvs. supply voltage VCC1.5Normalized

access

time1.41.31.21.11.00.90.8–551.41.2Normalized

ICC1.00.80.60.40.2Normalized supply current ICCvs. cycle frequency 1/tRC, 1/tWCTa = 25° CVCC = VCC(NOMINAL)VCC = VCC(NOMINAL)Ta = 25° CNOMINALSupply voltage (V)Output source current IOHvs. output voltage VOHMAX–103580125Ambient temperature (°C)Output sink current IOLvs. output voltage VOL0.00255075Cycle frequency (MHz)100140Output

source

current

(mA)1200140Output

sink

current

(mA)12003530Change

in

tAA

(ns)2520151050VCC0Typical access time change ∆tAAvs. output capacitive loadingVCC = VCC(NOMINAL)PLTa = 25° CVCC = VCC(NOMINAL)Ta = 25° CVCC = VCC(NOMINAL)Output voltage (V)VCCOutput voltage (V)250500750Capacitance (pF)10001/13/05; v.1.9Alliance SemiconductorP. 8 of 10

AS7C4098AS7C34098®Package dimensions444342423c44-pin TSOP 2eHe2dA2A1bEl0–5°AAA1A2bcdeHeEl44-pin TSOP 2Min (mm)Max (mm)1.20.050.150.951.050.300.450.210.1218.3118.5210.0610.2611.6811.940.80 (typical)0.400.60e44-pin SOJPin 1BA1bDE1E2cASeatingPlaneA2EAA1A2BbcDEE1E2e44-pin SOJ 400 milsMin(mils)Max(mils)0.1280.1480.025-0.1050.1150.0260.0320.0150.0200.0070.0131.1201.1300.370 NOM0.3950.4050.4350.4450.050 NOM1/13/05; v.1.9Alliance SemiconductorP. 9 of 10

AS7C4098AS7C34098®Ordering CodesPackageVersion5V commercialSOJ5V industrial3.3V commercial3.3V industrial5V commercialTSOP 25V industrial3.3V commercial3.3V industrialNote:Add suffix “N” to the above part number for lead free devices, Ex. AS7C4098-12JCN10 nsNANAAS7C34098-10JCNANANAAS7C34098-10TCNA12 nsAS7C4098-12JCAS7C4098-12JIAS7C34098-12JCAS7C34098-12JIAS7C4098-12TCAS7C4098-12TIAS7C34098-12TCAS7C34098-12TI15 nsAS7C4098-15JCAS7C4098-15JIAS7C34098-15JCAS7C34098-15JIAS7C4098-15TCAS7C4098-15TIAS7C34098-15TCAS7C34098-15TI20 nsAS7C4098-20JCAS7C4098-20JIAS7C34098-20JCAS7C34098-20JIAS7C4098-20TCAS7C4098-20TIAS7C34098-20TCAS7C34098-20TIPart numbering systemAS7CSRAM prefixXVoltage:Blank: 5V CMOS3: 3.3V CMOS4098–XXJ or TPackages:J: SOJ 400 milT: TSOP 2

XNDevice Access

numbertimeTemperature ranges:C: Commercial, 0°C to 70°CLead free deviceI: Industrial, –40°C to 85°C1/13/05; v.1.9Alliance SemiconductorP. 10 of 10© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trade-marks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is underdevelopment, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operateas, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express orimplied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except asexpress agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase ofproducts from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its productsfor use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting sys-tems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.