ALLIANCE MEMORY AS6C1008 说明书

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAMFEATURESAccess time:55nsLow powerconsumption:Operating current:10 mA(TYP.)

Standby current: 1µA(TYP.)Single2.7V~5.5VpowersupplyFully Compatible with all Competitors 5V product

Fully Compatible with all Competitors 3.3V productFullystatic operationTri-stateoutputDataretentionvoltage:1.5V(MIN.)All products are ROHS CompliantPackage: 32-pin450milSOP32-pin600milP-DIP32-pin8mmx20mm TSOP-I32-pin8mmx13.4mm sTSOP36-ball6mmx8mm TFBGAGENERA LDESCRIPTIONThe AS6C1008 is a 1,048,57 6-bit low powerCMOS static random access memoryorganizedas131,072words bricated using veryhigh performance, highreliability CMO S technology. Itsstandby current is stable within the range ofoperating AS6C1008is well designedforverylowpowersystemapplications, andparticularlywellsuited forbattery AS6C1008 operates from a single power supplyof2.7V~5.5V..FUNCTIONAL BLOCK DIAGRAMPIN DESCRIPTIONSYMBOLDESCRIPTIONAddressInputsDataInputs/OutputsChip Enable InputsWrite Enable InputOutput Enable InputPower SupplyGroundNoConnectionVccVssA0-A16DQ0–DQ7DECODER128Kx8MEMORYARRAYCE#,CE2WE#OE#VCCVSSNCA0-A16DQ0-DQ7I/ODATACIRCUITCOLUMNI/OCE#CE2WE#OE#CONTROLCIRCUIT02/February/07, v 1.0Alliance Memory 1 of 14

February 2007

®AS6C1008128K X 8 BIT LOW POWER CMOS SRAMPIN CONFIGURATIONNCA16A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2VssSOP/P-DIP323191817VccA15CE2WE#A13A8A9A11OE#A10CE#DQ7DQ6DQ5DQ4DQ3A11A9A8A13WE#CE2A15VccNCA16A14A12A7A6A5A4323191817OE#A10CE#DQ7DQ6DQ5DQ4DQ3VssDQ2DQ1DQ0A0A1A2A3AS6C1008AS6C1008TSOP-I/sTSOPABCDEFGHA0DQ4DQ5VssVccDQ6A1A2CE2WE#NCA3A4A5A6A7A8DQ0DQ1VccVssNCNCDQ2A15DQ3A13A14DQ7OE#CE#A16A9A10A11A121234TFBGA56.02/February/07, v 1.0Alliance Memory 2 of 14

February 2007®

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008ABSOLUTE MAXIMUM RATINGS*PARAMETER

Terminal Voltage with Respect to VSS

Operating Temperature

Storage Temperature

Power Dissipation

DC Output Current

Soldering Temperature (under 10 sec)

SYMBOL

VTERM

TATSTG

PD

IOUT

TSOLDER

RATING

-0.5 to 7.0

0 to 70(C grade)

UNIT

V

ºC-40 to 85(I grade)

-65 to 150

ºC1 W

50 mA

260 ºC*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stressrating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLEMODEStandby

Output Disable

Read

Write

CE#

H

X

L

L

L

CE2

X

L

H

H

H

OE#X

X

H

L

X

WE#X

X

H

H

L

I/O OPERATION

High-Z

High-Z

High-Z

DOUT

DIN

SUPPLY CURRENTISB1ISB1ICC,ICC1ICC,ICC1ICC,ICC1Note: H = VIH, L = VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICSSYMBOL TEST CONDITION MIN.

PARAMETER

Supply Voltage VCC 2.7

*1Input High Voltage VIH 0.7*Vcc*2Input Low Voltage VIL - 0.2

VCC≧ VIN

≧ VSSInput Leakage Current ILI- 1

VCC≧ VOUT

≧ VSS,Output Leakage

ILO- 1

Current Output Disabled

Output High Voltage VOH IOH= -1mA 2.2

Output Low Voltage VOL IOL

= 2mA -

Cycle time = Min.

CE# = VIL and CE2 = VIH,- 55

ICC-

II/O = 0mA

Average Operating

Cycle time = 1µsPower supply Current

CE#≦0.2V and CE2≧VCC-0.2V,ICC1-

II/O = 0mA

other pins at 0.2V or VCC-0.2VCE# ≧VCC-0.2V C*-Standby Power

ISB1Supply Current

or CE2≦0.2V

I*-*C=Commercial temperature/I= Industrial temperatureTYP.

3.0

-

-

-

-

2.7

-

10

*4MAX.

5.5

VCC+0.3

0.6

1

1

-

0.4

60

UNIT

V

V

V

µAµAV

V

mA111

10

2050

mA

µAµA02/February/07, v 1.0Alliance Memory Inc.

Page 3 of 14

February 2007

®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAMNotes:1. VIH(max) = VCC+ 3.0Vfor pulsewidth lessthan 10ns.2. VIL(min) = VSS- 3.0V for pulsewidth less than 10ns.3. Over/Undershoot specifications are characterized, not 100% l valuesare included for reference only and are not guaranteed or l valued are measured at VCC= VCC(TYP.)andTA=25ºCCAPACITANCE(TA=25℃,f=1.0MHz)PARAMETERInputCapacitanceInput/OutputCapacitanceSYMBOLCINCI/OMIN.--MAX68UNITpFpFNote :Theseparameters areguaranteedby device characterization, but not production tested.

ACTESTCONDITIONSInputPulseLevelsInputRiseandFallTimesInputandOutputTimingReferenceLevelsOutputLoad0.2VtoVCC-0.2V3ns1.5VCL=30pF+1TTL,IOH/IOL=-1mA/2mAACELECTRICALCHARACTERISTICS(1)READCYCLEPARAMETERReadCycleTimeAddressAccessTimeChipEnableAccessTimeOutputEnableAccessTimeChipEnabletoOutputinLow-ZOutputEnabletoOutputinLow-ZChipDisabletoOutputinHigh-ZOutputDisabletoOutputinHigh-ZOutputHoldfromAddressChange(2)WRITECYCLEPARAMETERWriteCycleTimeAddressValidtoEndofWriteChipEnabletoEndofWriteAddressSet-upTimeWritePulseWidthWriteRecoveryTimeDatatoWriteTimeOverlapDataHoldfromEtACEtOEtCLZ*tOLZ*tCHZ*tOHZ*.55--55-55-3010-5--20-2010-UNITnsnsnsnsnsnsnsnsnsSYM.

tWCtAWtCWtAStWPtWRtDWtDHtOW*tWHZ*.55-50-50-0-45-0-25-0-5--20UNITnsnsnsnsnsnsnsnsnsns*Theseparameters are guaranteedby device characterization, but not production tested.02/February/07, v 1.0Alliance Memory 4 of 14

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAM

TIMINGWAVEFORMSREADCYCLE1(AddressControlled)(1,2)tRCAddresstAADoutPreviousDataValidtOHDataValidREADCYCLE2(CE#andCE2andOE#Controlled)(1,3,4,5)

tRCAddresstAACE#tACECE2OE#tOLZtOEtOHtOHZtCHZData ValidHigh-ZtCLZDoutHigh-ZNotes:# is high for read iscontinuouslyselectedOE#=low,CE#=low.,CE2=s must be valid prior toor coincidentwithCE#= low,CE2= high; otherwise tAA is the , tOLZ, tCHZand tOHZ are specifiedwith CL= tion ismeasured ±500mV from steadystate.

any given temperature and voltage condition, tCHZislessthan tCLZ , tOHZ is less than tOLZ.02/February/07, v 1.0Alliance Memory 5 of 14

February 2007

®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAM

WRITECYCLE1(WE#Controlled)(1,2,3,5,6)tWCAddresstAWCE#tCWCE2tASWE#tWHZDout(4)High-ZtDWDintDHTOW(4)tWPtWRDataValidWRITECYCLE2(CE#andCE2Controlled)(1,2,5,6)tWCAddresstAWCE#tAStCWCE2tWPWE#tWHZDout(4)High-ZtDWDintDHtWRDataValidNotes:#, CE#must be high or CE2 must be low during all address occurs during the overlap of a low CE#, high CE2, low WE#.

a WE#controlledwritecyclewith OE# low, tWP must be greater than tWHZ+ tDW to allow the drivers to turn offand data tobeplaced on the this period, I/O pins are in the outputstate, and inputsignals must not be CE#lowtransition and CE2 high transition occurssimultaneouslywithor afterWE# lowtransition,the outputsremain in a high

and tWHZarespecifiedwithCL= tion is measured ±500mVfromsteadystate.02/February/07, v 1.0Alliance Memory 6 of 14

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAM

DATARETENTIONCHARACTERISTICSPARAMETERVCCforDataRetentionDataRetentionCurrentSYMBOLVDRIDRTESTCONDITIONCE#≧VCC-0.2VorCE2≦0.2VMIN.1.5TYP.-MAX.5.5UNITVC** - 0.5

VCC=1.5VCE#≧VCC-0.2VorCE2≦0.2V

I** 00tRC*-- 12 µA30--µAnsnsSeeDataRetentionChipDisabletoDatatCDRWaveforms(below)RetentionTimeRecoveryTimetRtRC*=ReadCycleTime C=Commercial temp/I = Industrial temp**DATARETENTIONWAVEFORMLowVccDataRetentionWaveform(1)(CE#controlled)VDR≧1.5VVccVcc(min.)tCDRCE#VIHCE#≧Vcc-0.2VVcc(min.)tRVIHLowVccDataRetentionWaveform(2)(CE2controlled)VDR≧1.5VVccVcc(min.)tCDRCE2CE2≦0.2VVILVILVcc(min.)tR02/February/07, v 1.0Alliance Memory 7 of 14

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAMPACKAGE OUTLINE DIMENSION32 pin 450 mil SOP Package Outline Dimension

SYM.

UNITINCH.(BASE)0.118 (MAX)

0.004(MIN)

0.111(MAX)

0.016(TYP)

0.008(TYP)

0.817(MAX)

0.445±0.005

0.555±0.012

0.050(TYP)

0.0347±0.0080.055±0.008

0.026(MAX)

0.004(MAX)

oo0 -10

MM(REF)

2.997 (MAX)

0.102(MIN)

2.82(MAX)

0.406(TYP)

0.203(TYP)

20.75(MAX)

11.303

±0.12714.097

±0.3051.270(TYP)

0.881

±0.203

1.397

±0.203

0.660 (MAX)

0.101(MAX)

oo0 -10AA1A2bcDEE1eLL1SyΘ02/February/07, v 1.0Alliance Memory 8 of 14

February 2007®

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

32 pin 600 mil P-DIP Package Outline Dimension

SYM.

UNIT

INCH(BASE) MM(REF)

0.001 (MIN)

0.150

± 0.005

0.018

± 0.005

1.650

± 0.005

0.600

± 0.010

0.544

± 0.004

0.100 (TYP)

0.640

± 0.020

0.130

± 0.010

0.075

± 0.010

0.070

± 0.005

0.254 (MIN)

3.810

± 0.127

0.457

± 0.127

41.910

± 0.12715.240

± 0.25413.818

± 0.1022.540 (TYP)

16.256

± 0.508.3.302

± 0.254

1.905

± 0.254

1.778

± 0.127

A1

A2

B

D

E

E1

e

eB

L

S

Q1

Note : D/E1/S dimension do not include mold flash.

02/February/07, v 1.0Alliance Memory 9 of 14

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS CH(BASE)0.047(MAX)0.004±0.0020.039±0.0020.008+0.002-0.0010.005(TYP)0.724±0.0040.315±0.0040.020(TYP)0.787±0.0080.0197±0.0040.0315±0.0040.003(MAX)oo0～5MM(REF)1.20(MAX)0.10±0.051.00±0.050.20+0.05-0.030.127(TYP)18.40±0.108.00±0.100.50(TYP)20.00±0.200.50±0.100.08±0.100.076(MAX)oo0～5AA1A2bcDEeHDLL1yΘ02/February/07, v 1.0Alliance Memory 10 of 14

February 2007®

128K X 8 BIT LOW POWER CMOS SRAM

AS6C1008

32pin8mmx13.4mm sTSOP PackageOutline DimensionHDcL12°(2x)13212°(2x)e1617"A"DSeatingPlanebEy12°(2X)1617GAUGEPLANEAA2c0.2540A1SEATING PLANE12°(2X)L1L"A" DETAIL CH(BASE)0.049(MAX)0.005±0.0020.039±0.0020.008±0.010.005(TYP)0.465±0.0040.315±0.0040.020(TYP)0.528±0.0080.0197±0.0040.0315±0.0040.003(MAX)oo0～5MM(REF)1.25(MAX)0.130±0.051.00±0.050.20±0.0250.127(TYP)11.80±0.108.00±0.100.50(TYP)13.40±0.20.0.50±0.100.8±0.100.076(MAX)oo0～5AA1A2bcDEeHDLL1yΘ02/February/07, v 1.0Alliance Memory 11 of 14

February 2007AS6C1008

128K X 8 BIT LOW POWER CMOS SRAM

36 ball 6mm × 8mm TFBGA PackageOutline Dimension02/February/07, v 1.0Alliance Memory 12 of 14

February 2007®AS6C1008

128K X 8 BIT LOW POWER CMOS SRAMORDERINGINFORMATIONOrdering CodesOperatingSpeedTemp nsCommercial ~

0º C to 70º C55Industrial ~

-40ºC to 85º C55Industrial ~

-40ºC to 85º C55Industrial ~

-40ºC to 85º C55Industrial ~

-40ºC to 85º C55AllianceAS6C1008-55PCNAS6C1008-55SINAS6C1008-55TINAS6C1008-55STINAS6C1008-55BINOrganizationVCC range128K X 8128K X 8128K X 8128K X 8128K X 82.7-5.5V2.7-5.5V2.7-5.5V2.7-5.5V2.7-5.5VPackage32pin 600mil PDIP32pin 450mil SOP32pin TSOP-I (8 x 20 mm)32pin sTSOP (8 x 13.4 mm)36pin TFBGA (6mm x 8mm)PartnumberingsystemAS6C1008-55XXNPackageOptions:P=32pin600milP-DIPlowDeviceS=32pin450milSOPpowerNumberT=32pinTSOP-I (8mm x 20 mm)SRAM10=1MAccessST=32pinsTSOP (8 x 13.4 mm)prefix08=by8TimeB=36ball6x8mmTFBGATemperatureRange:C=CommercialN=Lead(0ºCto+70ºC)FreeROHSI=IndustrialCompliant(-40ºto+85ºC)Part02/February/07, v 1.0Alliance Memory 13 of 14

February 2007AS6C1008128K X 8 BIT LOW POWER CMOS SRAM®®Alliance Memory, Inc.1116 South Amphlett, #2,

San Mateo, CA 94402Tel: 650-525-3737Fax:

Copyright © Alliance MemoryAll Rights ReservedPart Number: AS6C1008Document Version: v. 1.0© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to thisdocument and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The datacontained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at anytime, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inAlliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance'sTerms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofAlliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against allclaims arising from such use.02/February/07, v 1.0Alliance Memory 14 of 14